R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 1493
![IC SUPERH MPU ROMLESS 436-BGA](/photos/28/62/286211/436-bfbga_sml.jpg)
R8A77850ADBGV#RD0Z
Manufacturer Part Number
R8A77850ADBGV#RD0Z
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ADBGV#RD0Z
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77850ADBGV#RD0ZR8A77850ADBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Bit
23 to 16
15
14 to 12
11
10 to 8
Bit Name
AIV
DBE
SZ
ETBE
—
Initial
Value
All 0
0
All 0
0
All 0
R/W
R/W
R/W
R/W
R/W
R
Description
ASID Specify
Specifies the ASID value to be included in the match
conditions.
Data Value Enable*
Specifies whether or not to include the data value in the
match condition. This bit is valid only when the operand
access cycle is specified as a match condition.
0: The data value is not included in the match
1: The data value is included in the match conditions.
Operand Size Select
Specifies the operand size to be included in the match
conditions. This bit is valid only when the operand
access cycle is specified as a match condition.
000: The operand size is not included in the match
001: Byte access
010: Word access
011: Longword access
100: Quadword access*
Others: Reserved (setting prohibited)
Execution Count Value Enable
Specifies whether or not to include the execution count
value in the match conditions. If this bit is 1 and the
match condition satisfaction count matches the value
specified by the CETR1 register, the operation specified
by the CRR1 register is performed.
0: The execution count value is not included in the
1: The execution count value is included in the match
Reserved
For read/write in this bit, refer to General Precautions
on Handling of Product.
conditions; thus, not checked.
match conditions; thus, not checked.
conditions.
condition; thus, not checked (any operand size
specifies the match condition). *
Rev.1.00 Jan. 10, 2008 Page 1461 of 1658
3
2
29. User Break Controller (UBC)
1
REJ09B0261-0100
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