R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 1137
![IC SUPERH MPU ROMLESS 436-BGA](/photos/28/62/286211/436-bfbga_sml.jpg)
R8A77850ADBGV#RD0Z
Manufacturer Part Number
R8A77850ADBGV#RD0Z
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ADBGV#RD0Z
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77850ADBGV#RD0ZR8A77850ADBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Table 22.4 shows the operation in each transfer mode.
Table 22.4 Operation in Each Transfer Mode
Note:
Bit
7
6
5
4
3 to 0
Transfer Mode
Slave mode 1
Slave mode 2
Master mode 1
Master mode 2
*
Bit Name
TXDIZ
RCIM
SYNCAC
SYNCDL
⎯
The control data method is valid when the FL bits are set to 1xxx. (x: don't care.)
For details, see section 22.4.5, Control Data Interface.
Master/Slave
Slave
Slave
Master
Master
Initial
Value
0
0
0
0
All 0
R/W
R/W
R/W
R/W
R/W
R
SIOF_SYNC
Synchronous pulse
Synchronous pulse
Synchronous pulse
L/R
SIOF_TXD Pin Output when Transmission is Invalid*
Description
0: High output when invalid
1: High-impedance state when invalid
Note: Transmission is invalid when transmission is
Receive Control Data Interrupt Mode
0: Sets the RCRDY bit in SISTR when the contents of
1: Sets the RCRDY bit in SISTR each time when
SIOF_SYNC Pin Polarity
This bit is valid when the SIOF_SYNC signal is output
as synchronous pulse.
0: Active-high
1: Active-low
Data Pin Bit Delay for SIOF_SYNC Pin
This bit is valid when the SIOF_SYNC signal is output
as synchronous pulse. In slave mode, specify one-bit
delay.
0: No bit delay
1: 1-bit delay
Reserved
These bits are always read as 0. The write value should
always be 0.
SIRCR change.
SIRCR receives the control data.
disabled, or when a slot that is not assigned as
transmit data or control data is being
transmitted.
Bit Delay
SYNCDL bit
No
Rev.1.00 Jan. 10, 2008 Page 1105 of 1658
22. Serial I/O with FIFO (SIOF)
Slot position
Secondary FS
Slot position
Not supported
Control Data Method*
REJ09B0261-0100
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