R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 763
![IC SUPERH MPU ROMLESS 436-BGA](/photos/28/62/286211/436-bfbga_sml.jpg)
R8A77850ADBGV#RD0Z
Manufacturer Part Number
R8A77850ADBGV#RD0Z
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ADBGV#RD0Z
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77850ADBGV#RD0ZR8A77850ADBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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14.6.6
If the IWRRD, IWRRS, and IWW bits in CSnBCR are set to B'000 (no idle cycles), DACK of two
or more DMA transfers may be connected. If DACK of two or more DMA transfers is connected,
operation is not guaranteed under the following conditions. In these cases, set the IWRRD,
IWRRS, and IWW bits to B'001 to B'111 to insert a minimum of one idle cycle between DMA
transfers.
1. DMA transfer source is in the LBSC space, DMA transfer destination is not in the LBSC
2. DMA transfer source is not in the LBSC space, DMA transfer destination is in the LBSC
space, DACK output (CHCR.AM = 0) is set to a read cycle, and external request DREQ level
detection overrun 1 (cycle steal mode or burst mode) or external request DREQ edge detection
(cycle steal mode or burst mode) is set.
Prevent DACK of two or more DMA transfer units from connecting by setting the IWRRD
bits in CSnBCR to B'001 to B'111 (insert a minimum of one idle cycle in read-read cycles in
different space) and the IWRRS bits to B'001 to B'111 (insert a minimum of one idle cycle in
read-read cycles in the same space).
space, DACK output (CHCR.AM = 1) is set to a write cycle, and the external request DREQ
level detection overrun 1 (cycle steal mode or burst mode) or external request DREQ edge
detection (cycle steal mode or burst mode) is set.
Prevent DACK of two or more DMA transfer units from connecting by setting the IWW bits in
CSnBCR to B'001 to B'111 (insert a minimum of one idle cycle between write-read/write-
write cycles).
DACK/DREQ Setting
14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 731 of 1658
REJ09B0261-0100
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