R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 537

IC SUPERH MPU ROMLESS 436-BGA

R8A77850ADBGV#RD0Z

Manufacturer Part Number
R8A77850ADBGV#RD0Z
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77850ADBGV#RD0Z

Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

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12.4.12 DDRPAD Frequency Setting Register (DBFREQ)
The DDRPAD frequency setting register (DBFREQ) is a readable/writable register. It is initialized
only upon power-on reset.
Initial value:
Initial value:
Bit
31 to 9
8
7 to 3
R/W:
R/W:
BIt:
BIt:
Bit Name
DLLRST
31
15
R
R
0
0
30
14
R
R
0
0
29
13
Initial
Value
All 0
0
All 0
R
R
0
0
28
12
R
R
0
0
27
11
R
R
0
0
R/W
R
R/W
R
26
10
R
R
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
DLL Reset Bit
Resets the DLL within DDRPAD. The FREQ bits should
be used to set the frequency when this bit is 0. If the
FREQ bit is changed when this bit is 1, correct
operation cannot be guaranteed.
0: Resets the frequency setting
1: Generates or retains the frequency setting
Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
25
R
R
0
9
0
DLLRST
R/W
24
R
0
8
0
23
R
R
0
7
0
Rev.1.00 Jan. 10, 2008 Page 505 of 1658
22
R
R
0
6
0
12. DDR2-SDRAM Interface (DBSC2)
21
R
R
0
5
0
20
R
R
0
4
0
19
R
R
0
3
0
REJ09B0261-0100
FREQ2
R/W
18
R
0
2
0
FREQ1
R/W
17
R
0
1
0
FREQ0
R/W
16
R
0
0
0

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