R8A77850ADBGV#RD0Z Renesas Electronics America, R8A77850ADBGV#RD0Z Datasheet - Page 235
![IC SUPERH MPU ROMLESS 436-BGA](/photos/28/62/286211/436-bfbga_sml.jpg)
R8A77850ADBGV#RD0Z
Manufacturer Part Number
R8A77850ADBGV#RD0Z
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ADBGV#RD0Z
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77850ADBGV#RD0ZR8A77850ADBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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7.8.5
To enable the PMB to be managed by software, its contents are allowed to be read from and
written to by a P1 or P2 area program with a MOV instruction in privileged mode. The PMB
address array is allocated to addresses H'F610 0000 to H'F61F FFFF in the P4 area and the PMB
data array to addresses H'F710 0000 to H'F71F FFFF in the P4 area. VPN and V in the PMB can
be accessed as an address array, PPN, V, SZ, C, WT, and UB as a data array. V can be accessed
from both the address array side and the data array side. A program which executes a PMB
memory-mapped access should be placed in the page area at which the C bit in PMB is cleared to
0.
1. PMB address array read
2. PMB address array write
3. PMB data array read
4. PMB data array write
When memory reading is performed while bits 31 to 20 in the address field are specified as
H'F61 which indicates the PMB address array and bits 11 to 8 in the address field as an entry,
bits 31 to 24 in the data field are read as VPN and bit 8 in the data field as V.
When memory writing is performed while bits 31 to 20 in the address field are specified as
H'F61 which indicates the PMB address array and bits 11 to 8 in the address field as an entry,
and bits 31 to 24 in the data field are specified as VPN and bit 8 in the data field as V, data is
written to the specified entry.
When memory reading is performed while bits 31 to 20 in the address field are specified as
H'F71 which indicates the PMB data array and bits 11 to 8 in the address field as an entry, bits
31 to 24 in the data field are read as PPN, bit 9 in the data field as UB, bit 8 in the data field as
V, bits 7 and 4 in the data field as SZ, bit 3 in the data field as C, and bit 0 in the data field as
WT.
When memory writing is performed while bits 31 to 20 in the address field are specified as
H'F71 which indicates the PMB data array and bits 11 to 8 in the address field as an entry, and
bits 31 to 24 in the data field are specified as PPN, bit 9 in the data field as UB, bit 8 in the
data field as V, bits 7 and 4 in the data field as SZ, bit 3 in the data field as C, and bit 0 in the
data field as WT, data is written to the specified entry.
Memory-Mapped PMB Configuration
Rev.1.00 Jan. 10, 2008 Page 203 of 1658
7. Memory Management Unit (MMU)
REJ09B0261-0100
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