MRF89XA-I/MQ Microchip Technology, MRF89XA-I/MQ Datasheet - Page 47

• Manufacturer Part Number: MRF89XA-I/MQ
• Description: TXRX ISM SUB-GHZ ULP 32QFN
• Manufacturer: Microchip Technology

Specifications of MRF89XA-I/MQ

• Package / Case: 32-WFQFN Exposed Pad
• Frequency: 863MHz ~ 870MHz, 902MHz ~ 928MHz, 950MHz ~ 960MHz
• Data Rate - Maximum: 200kbps
• Modulation Or Protocol: FSK, OOK
• Applications: ISM
• Power - Output: 12.5dBm
• Sensitivity: -113dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 3mA
• Current - Transmitting: 25mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 863 MHz to 870 MHz, 902 MHz to 928 MHz, 950 MHz to 960 MHz
• Interface Type: SPI
• Noise Figure: - 112 dBc
• Output Power: - 8.5 dBm, + 12.5 dBm
• Operating Supply Voltage: 2.1 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Data Rate: 256 Kbps
• Maximum Supply Current: 25 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2.16.3
REGISTER 2-19:
© 2010 Microchip Technology Inc.
bit 7
R = Readable bit
-n = Value at POR
r = Reserved
bit 7
bit 6
bit 5
bit 4-3
bit 2-1
bit 0
POLFILEN
R/W-0
SYNC CONTROL REGISTER
DETAILS
POLFILEN: Polyphase Filter Enable bit
This bit enables the polyphase filter in OOK Receive mode.
1 = Polyphase filter enabled
0 = Polyphase filter disabled (default)
BSYNCEN: Bit Synchronizer Enable bit
This bit controls the enabling and disabling of the bit synchronizer in Continuous receive mode.
1 = Bit Synchronizer disabled
0 = Bit Synchronizer enabled (default)
SYNCREN: SYNC Word Recognition Enable bit
1 = ON
0 = OFF (default)
SYNCWSZ<1:0>: SYNC Word Size bit
11 = 32 bits (default)
10 = 24 bits
01 = 16 bits
00 = 8 bits
SYNCTEN<1:0>: SYNC Word Tolerated Error Numbers
These bits indicate the number of errors tolerated in the SYNC word recognition.
11 = 3 Errors
10 = 2 Errors
01 = 1 Errors
00 = 0 Errors (default)
Reserved: Reserved bit; do not use
0 = Reserved (default)
BSYNCEN
R/W-0
SYNCREG: SYNC CONTROL REGISTER (ADDRESS:0x12) (POR:0x18)
W = Writable bit
‘1’ = Bit is set
SYNCREN
R/W-0
R/W-1
SYNCWSZ<1:0>
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-1
R/W-0
SYNCTEN<1:0>
x = Bit is unknown
MRF89XA
R/W-0
DS70622B-page 47
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r
bit 0