MRF89XA-I/MQ Microchip Technology, MRF89XA-I/MQ Datasheet - Page 64

• Manufacturer Part Number: MRF89XA-I/MQ
• Description: TXRX ISM SUB-GHZ ULP 32QFN
• Manufacturer: Microchip Technology

Specifications of MRF89XA-I/MQ

• Package / Case: 32-WFQFN Exposed Pad
• Frequency: 863MHz ~ 870MHz, 902MHz ~ 928MHz, 950MHz ~ 960MHz
• Data Rate - Maximum: 200kbps
• Modulation Or Protocol: FSK, OOK
• Applications: ISM
• Power - Output: 12.5dBm
• Sensitivity: -113dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 3mA
• Current - Transmitting: 25mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 863 MHz to 870 MHz, 902 MHz to 928 MHz, 950 MHz to 960 MHz
• Interface Type: SPI
• Noise Figure: - 112 dBc
• Output Power: - 8.5 dBm, + 12.5 dBm
• Operating Supply Voltage: 2.1 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Data Rate: 256 Kbps
• Maximum Supply Current: 25 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.3.6
3.3.6.1
In OOK mode, the PA ramp times can be accurately
controlled
(PACONREG<4:3>). These bits directly control the slew
rate of the PARS pin.
TABLE 3-2:
FIGURE 3-4:
DS70622B-page 64
MRF89XA
PARC<1:0>
00
01
10
11
POWER AMPLIFIER
Rise and Fall Time Control
through
POWER AMPLIFIER
RISE/FALL TIMES
PA TIMING CONTROL
8.5 µs
t
15 µs
23 µs
PARS
3 µs
the
PARS
PA Output
Power
DATA
[V]
PARC<1:0>
60 dB
95%
(rise / fall)
20 / 10 µs
2.5 / 2 µs
10 / 6 µs
5 / 3 µs
t
PAOUT
t PARS
t PA_OUT
Preliminary
bits
3.3.7
The registers associated with Transmit mode are:
• GCONREG (Register 2-1)
• DMODREG (Register 2-2)
• FDEVREG (Register 2-3)
• BRSREG (Register 2-4)
• R1CREG (Register 2-7)
• P1CREG (Register 2-8)
• S1CREG (Register 2-9)
• R2CREG (Register 2-10)
• P2CREG (Register 2-11)
• S2CREG (Register 2-12)
• PACREG (Register 2-13)
• FTXRXIREG (Register 2-14)
• FTPRIREG (Register 2-15)
During the Transmit mode of MRF89XA, the Shift reg-
ister takes bytes from the FIFO and outputs them seri-
ally (MSb first) at the programmed bit rate to the
modulator. When the transmitter is enabled, it starts
sending out data from the Shift register with respect to
the set bit rate. After power-up and with the Transmit
registers enabled, the transmitter preloads the FIFO
with preambles before sending the actual data based
on the mode of operation. Figure 3-4 illustrates the PA
Control Timing.
t PARS
t PA_OUT
60 dB
95%
TRANSMIT MODE REGISTERS
© 2010 Microchip Technology Inc.