ML610Q412P-NNNTB03A7 Rohm Semiconductor, ML610Q412P-NNNTB03A7 Datasheet
ML610Q412P-NNNTB03A7
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ML610Q412P-NNNTB03A7 Summary of contents
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ML610Q411/Q412/Q415 User’s Manual FEUL610Q411-01 Issue Date: May. 1, 2010 ...
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NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application ...
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This manual describes the operation of the hardware of the 8-bit microcontroller ML610Q411/ML610Q412/ML610Q415. The following manuals are also available. Read them as necessary. nX-U8/100 Core Instruction Manual Description on the basic architecture and the each instruction of the MACU8 Assembler ...
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Classification Notation ♦ Numeric value xxh, xxH xxb ♦ Unit word, W byte, B nibble, N maga-, M kilo-, K kilo-, k milli-, m micro-, µ nano-, n second, s (lower case) ♦ Terminology “H” level, “1” level “L” level, ...
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Chapter 1 1. Overview ........................................................................................................................................................ 1-1 1.1 Features....................................................................................................................................................... 1-1 1.2 Configuration of Functional Blocks............................................................................................................ 1-4 1.2.1 Block Diagram of ML610Q411/ML610Q415 .................................................................................... 1-4 1.2.2 Block Diagram of ML610Q412.......................................................................................................... 1-5 1.3 Pins ............................................................................................................................................................. 1-6 1.3.1 Pin Layout........................................................................................................................................... 1-6 1.3.1.1 Pin Layout of ...
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Block Control Register 2 (BLKCON2) .............................................................................................. 4-7 4.2.7 Block Control Register 3 (BLKCON3) .............................................................................................. 4-8 4.2.8 Block Control Register 4 (BLKCON4) .............................................................................................. 4-9 4.3 Description of Operation........................................................................................................................... 4-11 4.3.1 Program Run Mode........................................................................................................................... 4-11 4.3.2 HALT Mode ..................................................................................................................................... 4-11 4.3.3 ...
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External Clock Input Mode ........................................................................................................... 6-10 6.3.2.3 Operation of High-Speed Clock Generation Circuit...................................................................... 6-11 6.3.3 Switching of System Clock............................................................................................................... 6-13 6.4 Specifying port registers ........................................................................................................................... 6-15 6.4.1 Functioning P21 (OUTCLK) as the high speed clock output ........................................................... 6-15 6.4.2 ...
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List of Registers ................................................................................................................................ 10-3 10.2.2 Timer 0 Data Register (TM0D) ........................................................................................................ 10-4 10.2.3 Timer 1 Data Register (TM1D) ........................................................................................................ 10-5 10.2.4 Timer 2 Data Register (TM2D) ........................................................................................................ 10-6 10.2.5 Timer 3 Data Register (TM3D) ........................................................................................................ 10-7 10.2.6 Timer ...
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List of Pins........................................................................................................................................ 13-2 13.2 Description of Registers............................................................................................................................ 13-3 13.2.1 List of Registers ................................................................................................................................ 13-3 13.2.2 Serial Port Transmit/Receive Buffers (SIO0BUFL, SIO0BUFH) .................................................... 13-4 13.2.3 Serial Port Control Register (SIO0CON).......................................................................................... 13-5 13.2.4 Serial Port Mode Register 0 (SIO0MOD0)....................................................................................... 13-6 ...
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Start Condition............................................................................................................................... 15-9 15.3.1.2 Restart Condition........................................................................................................................... 15-9 15.3.1.3 Slave Address Transmit Mode....................................................................................................... 15-9 15.3.1.4 Data Transmit Mode...................................................................................................................... 15-9 15.3.1.5 Data Receive Mode ....................................................................................................................... 15-9 15.3.1.6 Control Register Setting Wait State............................................................................................... 15-9 15.3.1.7 Stop Condition............................................................................................................................... 15-9 15.3.2 Communication Operation Timing ...
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Chapter 19 19. Port 2............................................................................................................................................................. 19-1 19.1 Overview................................................................................................................................................... 19-1 19.1.1 Features............................................................................................................................................. 19-1 19.1.2 Configuration .................................................................................................................................... 19-1 19.1.3 List of Pins........................................................................................................................................ 19-1 19.2 Description of Registers............................................................................................................................ 19-2 19.2.1 List of Registers ................................................................................................................................ 19-2 19.2.2 Port 2 Data Register (P2D) ............................................................................................................... 19-3 ...
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Port A Data Register (PAD) ............................................................................................................. 22-3 22.2.3 Port A Direction Register (PADIR) .................................................................................................. 22-4 22.2.4 Port A Control Registers 0, 1 (PACON0, PACON1) ....................................................................... 22-5 22.3 Description of Operation........................................................................................................................... 22-7 22.3.1 Input/Output Port Functions ............................................................................................................. 22-7 Chapter 23 ...
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SA-ADC Result Register 1H (SADR1H) ......................................................................................... 25-5 25.2.6 SA-ADC Control Register 0 (SADCON0) ....................................................................................... 25-6 25.2.7 SA-ADC Control Register 1 (SADCON1) ....................................................................................... 25-7 25.2.8 SA-ADC Mode Register 0 (SADMOD0) ......................................................................................... 25-8 25.3 Description of Operation........................................................................................................................... 25-9 25.3.1 Settings of ...
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Appendixes Appendix A Registers......................................................................................................................................... A-1 Appendix B Package Dimensions........................................................................................................................B-1 Appendix C Electrical Characteristics .................................................................................................................C-1 Appendix D Application Circuit Example.......................................................................................................... D-1 Appendix E Check List........................................................................................................................................E-1 Revision History Revision History .....................................................................................................................................................R-1 ML610Q411/ML610Q412/ML610Q415 User’s Manual Contents – 10 Contents ...
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Chapter 1 Overview ...
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Overview 1.1 Features This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as synchronous 2 serial port, UART bus interface (master), buzzer driver, battery level detect circuit, RC oscillation type A/D converter, ...
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Interrupt function ML610Q411/Q412: 10 Hz/1 Hz interrupt ML610Q415: 9.5Hz/0.95Hz interrupt • Capture − Time base capture × 2 channels ML610Q411/Q412: 4096 ML610Q415: 3906Hz∼30.5H • PWM − Resolution 16 bits × 1 ...
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LCD driver − The number of segments ML610Q411: 144 dots max. (36 seg × 4 com) ML610Q412: 176 dots max. (44 seg × 4 com) ML610Q415: 144 dots max. (36 seg × 4 com) − 1/1 to 1/4 duty ...
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... ML610Q415-xxxWA (Blank product: ML610Q415-NNNWA) − 120-pin plastic LQFP ML610Q411-xxxTBZ03A (Blank product: ML610Q411-NNNTBZ03A) ML610Q412-xxxTBZ03A (Blank product: ML610Q412-NNNTBZ03A) ML610Q412P-xxxTBZ03A（Blank product：ML610Q412P-NNNTBZ03A） ML610Q415-xxxTBZ03A (Blank product: ML610Q415-NNNTBZ03A) xxx: ROM code number P: Wide range temperature version A: Low-speed clock oscillation stop detection reset different spec version (See the user’s manual for more detail.) ...
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Configuration of Functional Blocks 1.2.1 Block Diagram of ML610Q411/ML610Q415 "*" indicates the secondary or tertiary function of each port. "*" indicates ML610Q415 does not have the crystal oscillation. EPSW1∼3 PSW Timing Controller On-Chip ICE RESET_N ...
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Block Diagram of ML610Q412 "*" indicates the secondary or tertiary function of each port. EPSW1∼3 PSW Timing Controller Instruction On-Chip ICE RESET_N RESET & TEST TEST XT0 XT1 OSC0* OSC LSCLK* OUTCLK* V DDL Power ...
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Pins 1.3.1 Pin Layout 1.3.1.1 Pin Layout of ML610Q411/ML610Q415 120pin TQFP Package 90pin 91pin 91 SEG21 92 SEG22 93 SEG23 SEG24 94 SEG25 95 SEG26 96 SEG27 97 98 SEG28 99 SEG29 100 SEG30 SEG31 101 SEG32 102 SEG33 ...
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Pin Layout of ML610Q412 120pin TQFP Package 90pin 91pin 91 SEG21 92 SEG22 93 SEG23 SEG24 94 SEG25 95 SEG26 96 SEG27 97 98 SEG28 SEG29 99 100 SEG30 101 SEG31 SEG32 102 SEG33 103 SEG34 104 SEG35 105 ...
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Pin Layout of ML610Q411/ML610Q415 Chip SEG21 91 SEG22 92 SEG23 93 SEG24 94 SEG25 95 SEG26 96 SEG27 97 SEG28 98 SEG29 99 SEG30 100 SEG31 101 SEG32 102 SEG33 103 SEG34 104 SEG35 105 PA0 106 PA1 107 ...
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Pin Layout of ML610Q412 Chip SEG21 91 SEG22 92 SEG23 93 SEG24 94 SEG25 95 SEG26 96 SEG27 97 SEG28 98 SEG29 99 SEG30 100 SEG31 101 SEG32 102 SEG33 103 SEG34 104 SEG35 105 SEG43 106 SEG42 107 ...
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Pad Coordinates of ML610Q411/ML610Q415 Chip Table 1-1 Pad Coordinates of ML610Q411/ML610Q415 No. Name X(µm) VPP 1 -1230 VSS 2 -1150 P20 3 -1070 P21 4 -990 P22 5 -910 P40 6 -830 P41 7 -750 RESET_N 8 -670 P42 ...
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Pad Coordinates of ML610Q412 Chip No. Name X(µm) VPP 1 -1230 VSS 2 -1150 P20 3 -1070 P21 4 -990 P22 5 -910 P40 6 -830 P41 7 -750 RESET_N 8 -670 P42 9 -590 P43 10 -510 P44 ...
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List of Pins PAD Primary function No. Pin name I/O Function 2, Negative power supply pin V SS 24,45,47 Positive power supply pin 22 Power supply pin for internal logic (internally 23 V ...
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PAD Primary function No. Pin name I/O Function Input/output port 15 P30 I/O Input/output port 16 P31 I/O Input/output port 17 P34 I/O Input/output port 18 P32 I/O Input/output port 19 P33 I/O Input/output port 20 P35 I/O Input/output port ...
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PAD Primary function No. Pin name I/O Function LCD segment pin 73 SEG3 O LCD segment pin 74 SEG4 O LCD segment pin 75 SEG5 O LCD segment pin 76 SEG6 O LCD segment pin 77 SEG7 O LCD segment ...
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Description of Pins Pin name I/O System Reset input pin. When this pin is set to a “L” level, system reset mode is RESET_N I set and the internal section is initialized. When this pin is set to a ...
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Pin name I/O UART UART data output pin. This pin is used as the secondary function of the TXD0 O P43 pin. UART data input pin. This pin is used as the secondary function of the RXD0 I P42 or ...
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Pin name I/O RC oscillation type A/D converter Channel 0 oscillation input pin. This pin is used as the secondary function IN0 I of the P30 pin. Channel 0 reference capacitor connection pin. This pin is used as the CS0 ...
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Pin name I/O Power supply pin for programming Flash ROM. A pull-down resistor is V — PP internally connected. ML610Q411/ML610Q412/ML610Q415 User’s Manual Description 1 – 19 Chapter 1 Overview Primary/ Secondary/ Logic Tertiary — — ...
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Termination of Unused Pins Table 1-3 shows methods of terminating the unused pins. Pin DDX V REF XT0 XT1 AIN0, AIN1 C1, C2 RESET_N ...
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CPU and Memory Space Chapter 2 ...
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CPU and Memory Space 2.1 Overview This LSI includes OKI’s original 8-bit CPU nX-U8/100 and the memory model is “SMALL model” . For details of the CPU nX-U8/100, see “nX-U8/100 Core Instruction Manual”. 2.2 Program Memory Space The program ...
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Data Memory Space The data memory space of this LSI consists of the ROM window area, 1KByte RAM area and SFR area of Segment 0 and the ROM reference areas of the Segment 1 and Segment 8. The data ...
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Description of Registers 2.6.1 List of Registers Address Name 0F000H Data segment register ML610Q411/ML610Q412/ML610Q415 User’s Manual Chapter 2 CPU and Memory Space Symbol (Byte) Symbol (Word) DSR 2 – 3 R/W Size Initial value R/W 8 00H ...
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Data Segment Register (DSR) Address: 0F000H Access: R/W Access size: 8 bits Initial value: 00H 7 6 DSR R/W R/W R/W Initial value 0 0 DSR is a special function register (SFR) to retain a data segment. ...
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Chapter 3 Reset Function ...
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Reset Function 3.1 Overview This LSI has the five reset functions shown below. If any of the five reset conditions is satisfied, this LSI enters system reset mode. • Reset by the RESET_N pin • Reset by power-on detection ...
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Description of Registers 3.2.1 List of Registers Address Name 0F001H Reset status register 3.2.2 Reset Status Register (RSTAT) Address: 0F001H Access: R/W Access size: 8 bits Initial value: Undefined 7 6 RSTAT ― ― R/W R/W R/W Initial value ...
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Description of Operation 3.3.1 Operation of System Reset Mode System reset has the highest priority among all the processings and any other processing being executed up to then is cancelled. The system reset mode is set by any of ...
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MCU Control Function Chapter 4 ...
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MCU Control Function 4.1 Overview The operating states of this LSI are classified into the following 4 modes including system reset mode: System reset mode Program run mode HALT mode STOP mode For system reset mode, see Chapter 3, ...
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Description of Registers 4.2.1 List of Registers Address Name Stop code acceptor 0F008H 0F009H Standby control register Block control register 0 0F028H Block control register 1 0F029H 0F02AH Block control register 2 Block control register 3 0F02BH Block control ...
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Stop Code Acceptor (STPACP) Address: 0F008H Access: W Access size: 8 bits Initial value: (Undefined STPACP ― ― Initial value ― ― STPACP is a write-only special function register (SFR) that is used ...
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Standby Control Register (SBYCON) Address: 0F009H Access: W Access size: 8 bits Initial value: 00H 7 6 SBYCON ― ― Initial value 0 0 SBYCON is a special function register (SFR) to control operating mode of ...
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Block Control Register 0(BLKCON0) Address: 0F028H Access: R/W Access size: 8 bits Initial value: 00H 7 6 BLKCON0 ― ― R/W R/W R/W Initial value 0 0 BLKCON0 is a special function register (SFR) to make even more reducing ...
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Block Control Register 1(BLKCON1) Address: 0F029H Access: R/W Access size: 8 bits Initial value: 00H 7 6 BLKCON1 ― DCAPR R/W R/W R/W Initial value 0 0 BLKCON1 is a special function register (SFR) to make even more reducing ...
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Block Control Register 2(BLKCON2) Address: 0F02AH Access: R/W Access size: 8 bits Initial value: 00H 7 6 BLKCON2 DI2C0 ― R/W R/W R/W Initial value 0 0 BLKCON2 is a special function register (SFR) to make even more reducing ...
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Block Control Register 3(BLKCON3) Address: 0F02BH Access: R/W Access size: 8 bits Initial value: 00H 7 6 BLKCON3 ― ― R/W R/W R/W Initial value 0 0 BLKCON3 is a special function register (SFR) to make even more reducing ...
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Block Control Register 4(BLKCON4) Address: 0F02CH Access: R/W Access size: 8 bits Initial value: 00H 7 6 BLKCON4 ― DLCD R/W R/W R/W Initial value 0 0 BLKCON4 is a special function register (SFR) to make even more reducing ...
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DSAD (bit 0) The DSAD bit is used to control SA type A/D converter operation. When the DSAD bit is set to “1”, the circuits related to SA type A/D converter are reset and turned off. DSAD Enable operating ...
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Description of Operation 4.3.1 Program Run Mode The program run mode is the state where the CPU executes instructions sequentially. At power-on reset, RESET_N pin reset, low-speed oscillation stop detect reset, or WDT overflow reset, the CPU executes instructions ...
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STOP Mode The STOP mode is the state where low-speed oscillation and high-speed oscillation stop and the CPU and peripheral circuits stop the operation. When the stop code acceptor is enabled by writing “5nH”(n: an arbitrary value) and “0AnH”(n: ...
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STOP Mode When CPU Operates with High-Speed Clock When the CPU is operating with a high-speed clock and the STP bit of SBYCON is set to “1” with the stop code acceptor enabled, the STOP mode is entered and ...
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Note on Return Operation from STOP/HALT Mode The operation of returning from the STOP mode and HALT mode varies according to the interrupt level (ELEVEL) of the program status word (PSW), master interrupt enable flag (MIE), the contents of ...
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Block Control Function This LSI has a block control function, which resets and completely turns operating circuits of unused peripherals off to make even more reducing current consumption. When certain bits of block control registers are set to “1”, ...
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Chapter 5 Interrupts (INTs) ...
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Interrupts (INTs) 5.1 Overview This LSI has 25 interrupt sources (External interrupts: 5 sources, Internal interrupts: 20 sources) and a software interrupt (SWI). For details of each interrupt, see the following chapters: Chapter 7, “Time Base Counter” Chapter 9, ...
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Description of Registers 5.2.1 List of Registers Address Name 0F011H Interrupt enable register 1 0F012H Interrupt enable register 2 0F013H Interrupt enable register 3 0F014H Interrupt enable register 4 0F015H Interrupt enable register 5 0F016H Interrupt enable register 6 ...
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Interrupt Enable Register 1 (IE1) Address: 0F011H Access: R/W Access size: 8 bits Initial value: 00H 7 6 IE1 R/W R/W R/W Initial value 0 0 IE1 is a special function register (SFR) to control enable/disable for ...
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Interrupt Enable Register 2 (IE2) Address: 0F012H Access: R/W Access size: 8 bits Initial value: 00H 7 6 IE2 EI2C0 R/W R/W R/W Initial value 0 0 IE2 is a special function register (SFR) to control enable/disable for ...
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Interrupt Enable Register 3 (IE3) Address: 0F013H Access: R/W Access size: 8 bits Initial value: 00H 7 6 IE3 R/W R/W R/W Initial value 0 0 IE3 is a special function register (SFR) to control enable/disable for ...
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Interrupt Enable Register 4 (IE4) Address: 0F014H Access: R/W Access size: 8 bits Initial value: 00H 7 6 IE4 R/W R/W R/W Initial value 0 0 IE4 is a special function register (SFR) to control enable/disable for ...
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Interrupt Enable Register 5 (IE5) Address: 0F015H Access: R/W Access size: 8 bits Initial value: 00H 7 6 IE5 R/W R/W R/W Initial value 0 0 IE5 is a special function register (SFR) to control enable/disable for ...
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Interrupt Enable Register 6 (IE6) Address: 0F016H Access: R/W Access size: 8 bits Initial value: 00H 7 6 IE6 E32H R/W R/W R/W Initial value 0 0 IE6 is a special function register (SFR) to control enable/disable for ...
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Interrupt Enable Register 7 (IE7) Address: 0F017H Access: R/W Access size: 8 bits Initial value: 00H 7 6 IE7 R/W R/W R/W Initial value 0 0 IE7 is a special function register (SFR) to control enable/disable for ...
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Interrupt Request Register 0 (IRQ0) Address: 0F018H Access: R/W Access size: 8 bits Initial value: 00H 7 6 IRQ0 R/W R/W R/W Initial value 0 0 IRQ0 is a special function register (SFR) to request an interrupt ...
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Interrupt Request Register 1 (IRQ1) Address: 0F019H Access: R/W Access size: 8 bits Initial value: 00H 7 6 IRQ1 R/W R/W R/W Initial value 0 0 IRQ1 is a special function register (SFR) to request an interrupt ...
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Interrupt Request Register 2 (IRQ2) Address: 0F01AH Access: R/W Access size: 8 bits Initial value: 00H 7 6 IRQ2 QI2C0 R/W R/W R/W Initial value 0 0 IRQ2 is a special function register (SFR) to request an interrupt ...
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Interrupt Request Register 3 (IRQ3) Address: 0F01BH Access: R/W Access size: 8 bits Initial value: 00H 7 6 IRQ3 R/W R/W R/W Initial value 0 0 IRQ3 is a special function register (SFR) to request an interrupt ...
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Interrupt Request Register 4 (IRQ4) Address: 0F01CH Access: R/W Access size: 8 bits Initial value: 00H 7 6 IRQ4 R/W R/W R/W Initial value 0 0 IRQ4 is a special function register (SFR) to request an interrupt ...
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Interrupt Request Register 5 (IRQ5) Address: 0F01DH Access: R/W Access size: 8 bits Initial value: 00H 7 6 IRQ5 QTM3 R/W R/W R/W Initial value 0 0 IRQ5 is a special function register (SFR) to request an interrupt ...
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Interrupt Request Register 6 (IRQ6) Address: 0F01EH Access: R/W Access size: 8 bits Initial value: 00H 7 6 IRQ6 Q32H R/W R/W R/W Initial value 0 0 IRQ6 is a special function register (SFR) to request an interrupt ...
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Interrupt Request Register 7 (IRQ7) Address: 0F01FH Access: R/W Access size: 8 bits Initial value: 00H 7 6 IRQ7 R/W R/W R/W Initial value 0 0 IRQ7 is a special function register (SFR) to request an interrupt ...
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Description of Operation With the exception of the watchdog timer interrupt (WDTINT) and the NMI interrupt (NMINT), interrupt enable/disable for 19 sources is controlled by the master interrupt enable flag (MIE) and the individual interrupt enable registers (IE1 to ...
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Maskable Interrupt Processing When an interrupt is generated with the MIE flag set to “1”, the following processing is executed by hardware and the processing of program shifts to the interrupt destination. (1) Transfer the program counter (PC) to ...
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Notes on Interrupt Routine Notes are different in programming depending on whether a subroutine is called or not by the program in executing an interrupt routine, whether multiple interrupts are enabled or disabled, and whether such interrupts are maskable ...
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A-2: When a subroutine is called by the program in executing an interrupt routine A-2-1: When multiple interrupts are disabled • Processing immediately after the start of interrupt routine execution Specify the “PUSH LR” instruction to save the subroutine return ...
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State B: Non-maskable interrupt is being processed B-1: When no instruction is executed in an interrupt routine • Processing immediately after the start of interrupt routine execution Specify the RTI instruction to return the contents of the ELR register to ...
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Interrupt Disable State Even if the interrupt conditions are satisfied, an interrupt may not be accepted depending on the operating state. This is called an interrupt disabled state. See below for the interrupt disabled state and the handling of ...
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Clock Generation Circuit Chapter 6 ...
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Clock Generation Circuit 6.1 Overview The clock generation circuit generates and provides a low-speed clock (LSCLK), 2× low-speed clock (LSCLK2), a high-speed clock (HSCLK), a system clock (SYSCLK), and a high-speed output clock (OUTCLK). LSCLK×2, and HSCLK are time ...
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List of Pins Pin name I/O Pin for connecting a crystal for low-speed clock XT0 I (Connect to VSS on ML610Q415) Pin for connecting a crystal for low-speed clock XT1 O (Non connect on ML610Q415) Pin for an external ...
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Frequency Control Register 0 (FCON0) Address: 0F002H Access: R/W Access size: 8/16 bits Initial value: 33H 7 6 FCON0 R/W R/W R/W Initial value 0 0 FCON0 is a special function register (SFR) to control the high-speed ...
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Note: − To switch the mode of the high-speed clock generation circuit using the OSCM0 bit, stop the high-speed oscillation and set the system clock to the low-speed clock (set the ENOSC bit and SYSCLK of FCON1 to “0”). − ...
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Frequency Control Register 1 (FCON1) Address: 0F003H Access: R/W Access size: 8 bits Initial value: 03H 7 6 FCON1 R/W R R/W Initial value 0 0 FCON1 is a special function register (SFR) to control the high-speed ...
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Description of Operation 6.3.1 Low-Speed Clock 6.3.1.1 Low-Speed Clock Generation Circuit Figure 6-2 shows the configuration of the low-speed clock generation circuit. ML610Q411/ML610Q412: A low-speed clock generation circuit is provided with an external 32.768 kHz crystal. To match the ...
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Operation of Low-Speed Clock Generation Circuit ML610Q411/ML610Q412: The low-speed clock generation circuit is activated by the occurrence of power ON reset. A low-speed clock (LSCLK) is supplied to the peripheral circuits after the elapse of the low-speed oscillation start ...
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ML610Q415: The low speed clock(LSCLK) starts to be supplied at the same time as the high speed clock (HSCLK). See Chapter 6.3.2, “High-Speed Clock” for more detail about the high speed clock generation. The low-speed clock generation circuit stops the ...
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High-Speed Clock Setting of the OSCM0 bits of the frequency control register 0 (FCON0) allows selection of the 500 kHz RC oscillation mode or external clock input mode for the high-speed clock generation circuit. 6.3.2.1 500 kHz RC Oscillation ...
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External Clock Input Mode In external clock input mode, external clock is input from the P10/OSC0 pin. Figure 6-5 shows the circuit configuration in external clock input mode. External clock input Figure 6-5 Circuit Configuration in External Clock Input ...
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Operation of High-Speed Clock Generation Circuit The high-speed clock generation circuit is activated in 500Hz RC oscillation mode by power-on reset generation result of the occurrence of power-on reset, the circuit goes into system reset mode and ...
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Figure 6-7 shows the waveforms of the high-speed clock generation circuit in crystal/ceramic oscillation mode. High-speed oscillation enable ENOSC T High-speed oscillation waveform High-speed oscillation Count: 8192 High-speed clock HSCLK Low-speed clock oscillation waveform Start of high-speed oscillation Figure 6-7 ...
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Switching of System Clock The system clock can be switched between high-speed clock (HSCLK) and low-speed clock (LSCLK) by using the frequency control registers (FCON0, FCON1). This function is not available on ML610Q415. Figure 6-8 shows a flow of ...
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System clock switching Use 500 kHz RC ? Yes Voltage detection by BLD VDD ≥ 1.3V? Yes ENOSC←”1” Wait until oscillation stabilizes (T SYSCLK←”1” High-speed operation mode Figure 6-9 Flow of System Clock Switching Processing (LSCLK→HSCLK) Note: − The function ...
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Specifying port registers When you want to make sure clock output functions are working, please check related port registers are specified. See Chapter 20, “Port2” for detail about the port registers. 6.4.1 Functioning P21 (OUTCLK) as the high speed ...
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Functioning P22 (LSCLK) as the low speed clock output Set P22MD bit (bit2 of P2MOD register) to “1” for specifying the low speed clock output as the secondary function of P22. Reg. name Bit 7 - Bit name Data ...
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Time Base Counter Chapter 7 ...
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Time Base Counter 7.1 Overview This LSI includes a low-speed time base counter (LTBC) and a high-speed time base counter (HTBC) that generate base clocks for peripheral circuits. By using the time base counter possible to generate ...
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HSCLK (500kHz) RESET (Internal signal) Data bus HTBDR: High-speed time base counter frequency divide register Figure 7-2 Configuration of High-Speed Time Base Counter Note: The frequency of HSCLK changes according to specified data in SYSC1 bit and SYSC0 bit of ...
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Description of Registers 7.2.1 List of Registers Address Name Low-speed time base counter 0F00AH register High-speed time base counter 0F00BH frequency divide register Low-speed time base counter 0F00CH frequency adjustment register L Low-speed time base counter 0F00DH frequency adjustment ...
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Low-Speed Time Base Counter (LTBR) Address: 0F00AH Access: R/W Access size: 8 bits Initial value: 00H 7 6 LTBR T1HZ T2HZ R/W R/W R/W Initial value 0 0 LTBR is a special function register (SFR) to read the T128HZ-T1HZ ...
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High-Speed Time Base Counter Divide Register (HTBDR) Address: 0F00BH Access: R/W Access size: 8 bits Initial value: 00H 7 6 HTBDR R/W R/W R/W Initial value 0 0 HTBDR is a special function register (SFR) to set ...
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Low-Speed Time Base Counter Frequency Adjustment Registers L and H (LTBADJL, LTBADJH) Address: 0F00CH Access: R/W Access size: 8/16 bits Initial value: 00H 7 6 LTBADJL LADJ7 LADJ6 R/W R/W R/W Initial value 0 0 Address: 0F00DH Access: R/W ...
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Description of Operation 7.3.1 Low-Speed Time Base Counter The low-speed time base counter (LTBC) starts counting from 0000H on the LSCLK falling edge after system reset. The T128HZ, T32HZ, T16HZ, and T2HZ outputs of LTBC are used as time ...
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High-Speed Time Base Counter The high-speed time base counter is configured as a 4-bit 1/n counter ( 16). In the 4-bit 1/n counter, the divided clock (1/16×HSCLK to 1/1×HSCLK) selected by the high-speed time base counter ...
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Low-Speed Time Base Counter Frequency Adjustment Function Frequency adjustment (Adjustment range: Approx. −488ppm to +488ppm. Adjustment accuracy: Approx. 0.48ppm) is possible for outputs of T8KHZ to T1HZ of LTBC by using the low-speed time base counter frequency adjust registers ...
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A signal generation for 16bit timer 2-3 frequency measurement mode A signal (437C) used for 16bit timer 2-3 frequency measurement mode is generated in the time base conter block. See Chapter 10, “Timer” for more detail about the frequency ...
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Chapter 8 Capture ...
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Capture 8.1 Overview This LSI has two channels of capture circuits that capture the T4KHZ to T32HZ signals of the low-speed base counter (LTBC) to the capture register at the occurrence of P00 and P01 interrupts. The circuits capture ...
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Description of Registers 8.2.1 List of Registers Address Name 0F090H Capture control register 0F091H Capture status register 0F092H Capture data register 0 0F093H Capture data register 1 ML610Q411/ML610Q412/ML610Q415 User’s Manual Symbol (Byte) Symbol (Word) CAPCON CAPSTAT ...
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Capture Control Register (CAPCON) Address: 0F090H Access: R/W Access size: 8 bits Initial value: 00H 7 6 CAPCON R/W R/W R/W Initial value 0 0 CAPCON is a special function register (SFR) to control the capture circuit. ...
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Capture Status Register (CAPSTAT) Address: 0F091H Access: R/W Access size: 8 bits Initial value: 00H 7 6 CAPSTAT R/W R/W R/W Initial value 0 0 CAPSTAT is a special function register (SFR) to indicate a state of ...
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Capture Data Register 0 (CAPR0) Address: 0F092H Access: R/W Access size: 8 bits Initial value: 00H 7 6 CAPR0 CP07 CP06 R/W R/W R/W Initial value 0 0 CAPR0 is a register in which capture data is stored. The ...
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Capture Data Register 1 (CAPR1) Address: 0F093H Access: R/W Access size: 8 bits Initial value: 00H 7 6 CAPR1 CP17 CP16 R/W R/W R/W Initial value 0 0 CAPR1 is a register in which capture data is stored. The ...
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Description of Operation The capture circuit starts the capture operation by setting the ECAP0 or ECAP1 bit of the capture control register (CAPCON). When the input trigger from the P00 or P01 pin selected by the external interrupt control ...
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Timer (1kHzTM) Chapter 9 ...
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Timer (1kHzTM) 9.1 Overview This LSI includes a 1 kHz timer to measure 1/1000 seconds. The 1 kHz timer counts the 1 kHz(*) signal created by dividing the T2KHZ output frequency (*) of the low-speed time base ...
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Description of Registers 9.2.1 List of Registers Address Name 0F080H 1 kHz timer count register L 0F081H 1 kHz timer count register H 0F082H 1 kHz timer control register ML610Q411/ML610Q412/ML610Q415 User’s Manual Chapter 9 1 kHz Timer (1kHzTM) Symbol ...
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Timer Count Registers (T1KCRL, T1KCRH) Address: 0F080H Access: R/W Access size: 8/16 bits Initial value: 00H 7 6 T1KCRL T1KC3 T1K02 R/W R/W R/W Initial value 0 0 Address: 0F081H Access: R/W Access size: 8 bits Initial ...
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Timer Control Register (T1KCON) Address: 0F082H Access: R/W Access size: 8 bits Initial value: 00H 7 6 T1KCON R/W R/W R/W Initial value 0 0 T1KCON is a special function register (SFR) to control the ...
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Description of Operation By setting the T1KRUN bit of the 1kHz timer control register (T1KCON) to “1”, the 1kHz timer starts counting of the 1kHz timer counter registers (T1KCRL, T1KCRH). By dividing the T2KHz signal frequency ...
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Chapter 10 Timers ...
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Timers 10.1 Overview This LSI includes 4 channels of 8-bit timers. For the input clock, see Chapter 6, “Clock Generation Circuit”. 10.1.1 Features • The timer interrupt (TMnINT) is generated when the values of timer counter register (TMnC, n=0 ...
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Low-speed Timer Base Counter(LTBC) Counter External clock P44/T02P0CK P45/T13P1CK (c ) Frequency measurement mode with 16bit timer(Timer2 to 3) ML610Q411/ML610Q412/ML610Q415 User’s Manual 16KHz 8KHz 436cycle 4KHz at 2KHz 32KHz 1KHz Decoder D Q 512Hz 256Hz 128Hz 64Hz 64Hz 437c LSCLK ...
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Description of Registers 10.2.1 List of Registers Address Name Timer 0 data register 0F030H 0F031H Timer 0 counter register 0F032H Timer 0 control register 0 Timer 0 control register 1 0F033H Timer 1 data register 0F034H 0F035H Timer 1 ...
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Timer 0 Data Register (TM0D) Address: 0F030H Access: R/W Access size: 8 bits Initial value: 0FFH 7 6 TM0D T0D7 T0D6 R/W R/W R/W Initial value 1 1 TM0D is a special function register (SFR) to set the value ...
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Timer 1 Data Register (TM1D) Address: 0F034H Access: R/W Access size: 8 bits Initial value: 0FFH 7 6 TM1D T1D7 T1D6 R/W R/W R/W Initial value 1 1 TM1D is a special function register (SFR) to set the value ...
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Timer 2 Data Register (TM2D) Address: 0F038H Access: R/W Access size: 8 bits Initial value: 0FFH 7 6 TM2D T2D7 T2D6 R/W R/W R/W Initial value 1 1 TM2D is a special function register (SFR) to set the value ...
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Timer 3 Data Register (TM3D) Address: 0F03CH Access: R/W Access size: 8 bits Initial value: 0FFH 7 6 TM3D T3D7 T3D6 R/W R/W R/W Initial value 1 1 TM3D is a special function register (SFR) to set the value ...
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Timer 0 Counter Register (TM0C) Address: 0F031H Access: R/W Access size: 8 bits Initial value: 00H 7 6 TM0C T0C7 T0C6 R/W R/W R/W Initial value 0 0 TM0C is a special function register (SFR) that functions as an ...
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Timer 1 Counter Register (TM1C) Address: 0F035H Access: R/W Access size: 8 bits Initial value: 00H 7 6 TM1C T1C7 T1C6 R/W R/W R/W Initial value 0 0 TM1C is a special function register (SFR) that functions as an ...
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Timer 2 Counter Register (TM2C) Address: 0F039H Access: R/W Access size: 8 bits Initial value: 00H 7 6 TM2C T2C7 T2C6 R/W R/W R/W Initial value 0 0 TM2C is a special function register (SFR) that functions as an ...
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Timer 3 Counter Register (TM3C) Address: 0F03DH Access: R/W Access size: 8 bits Initial value: 00H 7 6 TM3C T3C7 T3C6 R/W R/W R/W Initial value 0 0 TM3C is a special function register (SFR) that functions as an ...
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Timer 0 Control Register 0 (TM0CON0) Address: 0F032H Access: R/W Access size: 8 bits Initial value: 00H 7 6 TM0CON0 R/W R/W R/W Initial value 0 0 TM0CON0 is a special function (SFR) to control a timer ...
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Timer 1 Control Register 0 (TM1CON0) Address: 0F036H Access: R/W Access size: 8 bits Initial value: 00H 7 6 TM1CON0 R/W R/W R/W Initial value 0 0 TM1CON0 is a special function (SFR) to control a timer ...
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Timer 2 Control Register 0 (TM2CON0) Address: 0F03AH Access: R/W Access size: 8 bits Initial value: 00H(ML610Q415), 0A0H(ML610Q411/ML610Q412 TM2CON0 T2FMA7 T2FMA6 R Initial value * * TM2CON0 is a special function (SFR) to control a ...
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Timer 3 Control Register 0 (TM3CON0) Address: 0F03EH Access: R/W Access size: 8 bits Initial value: 00H 7 6 TM3CON0 R/W R/W R/W Initial value 0 0 TM3CON0 is a special function (SFR) to control a timer ...
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Timer 0 Control Register 1 (TM0CON1) Address: 0F033 Access: R/W Access size: 8 bits Initial value: 00H 7 6 TM0CON1 T0STAT R/W R R/W Initial value 0 0 TM0CON1 is a special function register (SFR) to control a ...
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Timer 1 Control Register 1 (TM1CON1) Address: 0F037H Access: R/W Access size: 8 bits Initial value: 00H 7 6 TM1CON1 T1STAT R/W R R/W Initial value 0 0 TM1CON1 is a special function register (SFR) to control a ...
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Timer 2 Control Register 1 (TM2CON1) Address: 0F03BH Access: R/W Access size: 8 bits Initial value: 00H 7 6 TM2CON1 T2STAT R/W R R/W Initial value 0 0 TM2CON1 is a special function register (SFR) to control a ...
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Timer 3 Control Register 1 (TM3CON1) Address: 0F03FH Access: R/W Access size: 8 bits Initial value: 00H 7 6 TM3CON1 T3STAT R/W R R/W Initial value 0 0 TM3CON1 is a special function register (SFR) to control a ...
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Description of Operation 10.3.1 Timer mode operation The timer counters (TMnC) are set to an operating state (TnSTAT are set to “1”) on the first falling edge of the timer clocks (TnCK) that are selected by the Timer 0 ...
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The frequency measurement mode in 16-bit timer 2&3, is used to count the frequency of 500kHz RC oscillation clock which typically has temperature variation and production tolerance. Using the frequency measurement mode can ...
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Set “FFH” to both TM2D register and TM3D register. (5) Clear both TM2C register and TM3C register to “00H”. (6) Set T2RUN bit (bit0 of TM2CON1 register) to “1” to start counting the timer. (7) On the condition of ...
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For example, when the target baud-rate is 9600bps and the clock is HSCLK(500kHz), the UART0 baud-rate register (UA0BRTH, UA0BRTL) should be set as follows. See Section 14.3.2. in UART ...
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Chapter 11 PWM ...
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PWM 11.1 Overview This LSI includes one channel of 16-bit PWM (Pulse Width Modulation). The PWM output (PWM0) function is assigned to P43(Port 4) and P34(Port 3) as the tertiary function. For the functions of port 4 and port3, ...
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List of Pins Pin name I/O P43/PWM0 O P34/PWM0 O 11.2 Description of Registers 11.2.1 List of Registers Address Name PWM0 period register L 0F0A0H PWM0 period register H 0F0A1H 0F0A2H PWM0 duty register L PWM0 duty register H ...
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PWM0 Period Registers (PW0PL, PW0PH) Address: 0F0A0H Access: R/W Access size: 8 bits Initial value: 0FFH 7 6 PW0PL P0P7 P0P6 R/W R/W R/W At reset 1 1 Address: 0F0A1H Access: R/W Access size: 8 bits Initial value: 0FFH ...
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PWM0 Duty Registers (PW0DL, PW0DH PW0DL P0D7 P0D6 R/W R/W R/W At reset 0 0 Address: 0F0A2H Access: R/W Access size: 8 bits Initial value: 00H 7 6 PW0DH P0D15 P0D14 R/W R/W R/W At reset 0 ...
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PWM0 Counter Registers (PW0CH, PW0CL PW0CL P0C7 P0C6 R/W R/W R/W At reset 0 0 Address: 0F0A4H Access: R/W Access size: 8 bits Initial value: 00H 7 6 PW0DH P0C15 P0C14 R/W R/W R/W At reset 0 ...
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PWM0 Control Register 0 (PW0CON0 PW0CON0 R/W R/W R/W At reset 0 0 Address: 0F0A6H Access: R/W Access size: 8 bits Initial value: 00H PW0CON0 is a special function register (SFR) to control PWM. [Description ...
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PWM0 Control Register 1 (PW0CON1 PW0CON1 P0STAT P0FLG R/W R R/W At reset 0 1 Address: 0F0A7H Access: R/W Access size: 8 bits Initial value: 40H PW0CON1 is a special function register (SFR) to control PWM0. [Description ...
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Description of Operation The PWM0 counter registers (PW0CH, PW0CL) are set to an operating state (P0STAT is set to “1”) on the first falling edge of the PWM clock (P0CK) that are selected by the PWM0 control register 0 ...
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After the P0RUN bit is set to “1”, counting starts in synchronization with the PWM clock. This causes an error clock pulse to the time the first PWM interrupt is issued. The PWM interrupt period from ...
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Specifying port registers When you want to make sure the PWM function is working, please check related port registers are specified. See Chapter 22, “Port 4” and Chapter 21, “Port 3” for detail about the port registers. 11.4.1 Functioning ...
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Functioning P34 (PWM0) as the PWM output Set P34MD1 bit (bit4 of P3MOD1 register) to “1” and set P34MD0 bit (bit4 of P3MOD0 register) to “0”, for specifying the PWM output as the tertiary function of P34. Reg. name ...
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Chapter 12 Watchdog Timer ...
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Watchdog Timer 12.1 Overview This LSI incorporates a watchdog timer (WDT) that operates at a system reset unconditionally (free-run operation) in order to detect an undefined state of the MCU and return from that state. If the WDT counter ...
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Description of Registers 12.2.1 List of Registers Address Name 0F00EH Watchdog timer control register 0F00FH Watchdog timer mode register ML610Q411/ML610Q412/ML610Q415 User’s Manual Chapter 12 Watchdog Timer Symbol (Byte) Symbol (Word) WDTCON WDTMOD 12 – 2 R/W Size ...
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Watchdog Timer Control Register (WDTCON) Address: 0F00EH Access: R/W Access size: 8 bits Initial value: 00H 7 6 WDTCON d7 d6 R/W R/W R/W Initial value 0 0 WDTCON is a special function register (SFR) to clear the WDT ...
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Watchdog Timer Mode Register (WDTMOD) Address: 0F00FH Access: R/W Access size: 8 bits Initial value: 02H 7 6 WDTMOD R/W R/W R/W Initial value 0 0 WDTMOD is a special function register to set the overflow period ...
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Description of Operation The WDT counter starts counting after the system reset has been released and the low-speed clock oscillation start.. Write "5AH" when the internal pointer (WDP) is "0"and then the WDT counter is cleared by writing "0A5H" ...
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Figure 12-2 shows an example of watchdog timer operation. Low-speed oscillation start RESET_S System reset Data: WDTCON Write WDTP Internal pointer WDT counter WDTINT WDT interrupt WDT reset Figure 12-2 Example of Watchdog Timer Operation 1 The WDT counter starts ...
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Synchronous Serial Port Chapter 13 ...
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Synchronous Serial Port 13.1 Overview This LSI includes one channel of the 8/16-bit synchronous serial port (SSIO) and can also be used to control the device incorporated with the SPI interface by using one GPIO as the chip enable ...
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List of Pins Pin name I/O P40/SIN0 I P44/SIN0 P41/SCK0 I/O P45/SCK0 P42/SOUT0 O P46/SOUT0 ML610Q411/ML610Q412/ML610Q415 User’s Manual Description Receive data input. Used for the tertiary function of the P40 and P44 pins. Synchronous clock input/output. Used for the ...
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Description of Registers 13.2.1 List of Registers Address Name Serial port 0 transmit/receive 0F280H buffer L Serial port 0 transmit/receive 0F281H buffer H 0F282H Serial port 0 control register Serial port 0 mode register 0 0F284H 0F285H Serial port ...
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Serial Port Transmit/Receive Buffers (SIO0BUFL, SIO0BUFH) Address: 0F280H Access: R/W Access size: 8 bits/16 bits Initial value: 00H 7 6 SIO0BUFL S0B7 S0B6 R/W R/W R/W Initial value 0 0 Address: 0F281H Access: R/W Access size: 8 bits Initial ...
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Serial Port Control Register (SIO0CON) Address: 0F282H Access: R/W Access size: 8 bits Initial value: 00H 7 6 SIO0CON R/W R/W R/W Initial value 0 0 SIO0CON is a special function register (SFR) to control the synchronous ...
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Serial Port Mode Register 0 (SIO0MOD0) Address: 0F284H Access: R/W Access size: 8 bits Initial value: 00H 7 6 SIO0MOD0 R/W R/W R/W Initial value 0 0 SIO0MOD0 is a special function register (SFR) to set mode ...
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Serial Port Mode Register 1 (SIO0MOD1) Address: 0F285H Access: R/W Access size: 8 bits Initial value: 00H 7 6 SIO0MOD1 R/W R/W R/W Initial value 0 0 SIO0MOD1 is a special function register (SFR) to set mode ...
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Description of Operation 13.3.1 Transmit Operation When “1” is written to the S0MD1 bit and “0” is written to the S0MD0 bit of the serial mode register (SIO0MOD0), this LSI is set to a transmit mode. When transmit data ...
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Receive Operation When “0” is written to the S0MD1 bit and “1” is written to the S0MD0 bit of the serial mode register (SIO0MOD0), this LSI is set to a receive mode. When the S0EN bit of the serial ...
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Transmit/Receive Operation When “1” is written to the S0MD1 bit and “1” is written to the S0MD0 bit of the serial mode register (SIO0MOD0), this LSI is set to a transmit/receive mode. When the S0EN bit of the serial ...
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Specifying port registers When you want to make sure the SSIO function is working, please check related port registers are specified. See Chapter 21, “Port 4” for detail about the port registers. 13.4.1 Functioning P42 (SOUT0), P41 (SCK0) and ...
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Functioning P42 (SOUT0), P41 (SCK0) and P40 (SIN0) as the SSIO/ ”Slave mode” Set P42MD1-P40MD1 bits(bit2-bit0 of P4MOD1 register) to “1” and set P42MD0-P40MD0(bit2-bit0 of P4MOD0 register) to “0”, for specifying the SSIO as the secondary function of P42, ...
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Functioning P46 (SOUT0), P45 (SCK0) and P44 (SIN0) as the SSIO/ ”Master mode” Set P46MD1-P44MD1 bits(bit6-bit4 of P4MOD1 register) to “1” and set P46MD0-P44MD0(bit6-bit4 of P4MOD0 register) to “0”, for specifying the SSIO as the secondary function of P46, ...
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Functioning P46 (SOUT0), P45 (SCK0) and P44 (SIN0) as the SSIO/ ”Slave mode” Set P46MD1-P44MD1 bits(bit6-bit4 of P4MOD1 register) to “1” and set P46MD0-P44MD0(bit6-bit4 of P4MOD0 register) to “0”, for specifying the SSIO as the secondary function of P46, ...
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Chapter 14 UART ...
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UART 14.1 Overview This LSI includes 1 channel of UART (Universal Asynchronous Receiver Transmitter) which is an asynchrnous serial interface. For the input clock, see Chapter 6, “Clock Generation Circuit”. The use of UART requires setting of the secondary ...
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Description of Registers 14.2.1 List of Registers Address Name 0F290H UART0 transmit/receive buffer 0F291H UART0 control register 0F292H UART0 mode register 0 0F293H UART0 mode register 1 0F294H UART0 baud rate register L 0F295H UART0 baud rate register H ...
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UART0 Transmit/Receive Buffer (UA0BUF) Address: 0F290H Access: R/W Access size: 8 bits Initial value: 00H 7 6 UA0BUF U0B7 U0B6 R/W R/W R/W Initial value 0 0 UA0BUF is a special function register (SFR) to store the transmit/receive data ...
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UART0 Control Register (UA0CON) Address: 0F291H Access: R/W Access size: 8 bits Initial value: 00H 7 6 UA0CON R/W R/W R/W Initial value 0 0 UA0CON is a special function register (SFR) to start/stop communication of the ...
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UART0 Mode Register 0 (UA0MOD0) Address: 0F292H Access: R/W Access size: 8/16 bits Initial value: 00H 7 6 UA0MOD0 — — R/W R/W R/W Initial value 0 0 UA0MOD0 is a special function register (SFR) to set the transfer ...
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UART0 Mode Register 1 (UA0MOD1) Address: 0F293H Access: R/W Access size: 8/16 bits Initial value: 00H 7 6 UA0MOD1 — U0DIR R/W R/W R/W Initial value 0 0 UA0MOD1 is a special function register (SFR) to set the transfer ...
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U0DIR (bit 6) The U0DIR bit is used to select LSB first or MSB first in the communication of the UART. U0DIR 0 LSB first (initial value) 1 MSB first Note: Always set the UA0MOD1 register while communication is ...
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UART0 Baud Rate Registers L, H (UA0BRTL, UA0BRTH) Address: 0F294H Access: R/W Access size: 8/16 bits Initial value: 0FFH 7 6 UA0BRTL U0BR7 U0BR6 R/W R/W R/W Initial value 1 1 Address: 0F295H Access: R/W Access size: 8 bits ...
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UART0 Status Register (UA0STAT) Address: 0F296H Access: R/W Access size: 8 bits Initial value: 00H 7 6 UA0STAT — — R/W R/W R/W Initial value 0 0 UA0STAT is a special function register (SFR) to indicate the state of ...
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U0FUL (bit 3) The U0FUL bit is used to indicate the state of the transmit/receive buffer of the UART. When transmit data is written in UA0BUF in transmit mode, this bit is set to “1” and when transmit data ...
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Description of Operation 14.3.1 Transfer Data Format In the transfer data format, one frame contains a start bit, a data bit, a parity bit, and a stop bit. In this format bits can be selected as ...
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Baud Rate Baud rates are generated by the baud generator. The baud rate generator generates a baud rate by counting the clock selected by the baud rate clock selection bits (U0CK1, U0CK0) of the UART0 mode register 0 (UA0MOD0). ...
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Transmit Data Direction Figure 14-4 shows the relationship between the transmit/receive buffer and the transmit/receive data. • Data length: 8 bits LSB reception U0B7 MSB reception • Data length: 7 bits LSB reception MSB reception • Data length: 6 ...
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Transmit Operation Transmission is started by setting the U0IO bit of the UART0 mode register 0 (UA0MOD0) to “0” to select transmit mode and setting the U0EN bit of the UART0 control register (UA0CON) to “1”. Figure 14-5 shows ...
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ML610Q411/ML610Q412/ML610Q415 User’s Manual Figure 14-5 Operation Timing in Transmission 14 – 15 Chapter 14 UART ...