ML610Q412P-NNNTB03A7 Rohm Semiconductor, ML610Q412P-NNNTB03A7 Datasheet - Page 86

• Manufacturer Part Number: ML610Q412P-NNNTB03A7
• Description: MCU 8BIT 16K FLASH 120-TQFP
• Manufacturer: Rohm Semiconductor

Specifications of ML610Q412P-NNNTB03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 625kHz
• Connectivity: I²C, SSP, UART/USART
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 2x12b, 2x24b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.
6.1
6.1.1
• Low-speed clock: 32.768 kHz crystal oscillation mode
ML610Q411/ML610Q412:
• High-speed clock: Software selection
6.1.2
The clock generation circuit generates and provides a low-speed clock (LSCLK), 2× low-speed clock (LSCLK2), a
high-speed clock (HSCLK), a system clock (SYSCLK), and a high-speed output clock (OUTCLK).
LSCLK×2, and HSCLK are time base clocks for the peripheral circuits, SYSCLK is a basic operation clock of CPU,
and OUTCLK is a clock that is output from a port.
For the OUTCLK output port, see Chapter 19, “Port 2”. Additionally, for the STOP mode described in this chapter, see
Chapter 4, “MCU Control Function”, and for BLD, see Chapter 27, “Battery Level Detection Circuit”.
Figure 6-1 shows the configuration of the clock generation circuit.
Note:
This LSI starts operation with a clock generated by dividing the 500 kHz RC oscillation frequency by 8 after power-on
or a system reset. At initialization by software, set the FCON0 or FCON1 register to switch the clock to a required
one. Operation of ML610Q411/ ML610Q412 is not guaranteed under a condition where a low-speed clock is not
supplied.
ML610Q411/ML610Q412:
− 32.768kHz Crystal oscillation mode
− Capable of generating LSCLK × 2 (64 kHz) to be used for some peripherals.
− 1/16 of 500kHz RC oscillation mode (31.25kHz)
− Capable of generating LSCLK × 2 (62.5kHz) to be used for some peripherals.
− 500 kHz RC oscillation mode
− External clock input mode (Not available on ML610Q415)
FCON0
FCON1
*
*
1
2
Clock Generation Circuit
Overview
P10/OSC0
P11/OSC1
Features
Configuration
XT0*
XT1*
: Frequency control register 0
: Frequency control register 1
:Not used on ML610Q415
:The SYSCLK is fixed to HSCLK on ML610Q415
1
1
clock generation
clock generation
High-speed
Low-speed
circuit
circuit
Figure 6-1 Configuration of Clock Generation Circuit
OSCLK
FCON0, FCON1
1/1, 1/2, 1/4, 1/8
1/1, 1/2, 1/4, 1/8
Divide ratio
Divide ratio
selection
selection
6 – 1
ML610Q411/ML610Q412/ML610Q415 User’s Manual
*
2
Chapter 6 Clock Generation Circuit
System clock
(SYSCLK)
2
(LSCLK
Low-speed clock
(LSCLK)
High-speed clock
(HSCLK)
High-speed output clock
(OUTCLK)
Data bus
×
low-speed clock
×
2)
LSCLK,