ML610Q412P-NNNTB03A7 Rohm Semiconductor, ML610Q412P-NNNTB03A7 Datasheet - Page 215

• Manufacturer Part Number: ML610Q412P-NNNTB03A7
• Description: MCU 8BIT 16K FLASH 120-TQFP
• Manufacturer: Rohm Semiconductor

Specifications of ML610Q412P-NNNTB03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 625kHz
• Connectivity: I²C, SSP, UART/USART
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 2x12b, 2x24b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.3 Description of Operation
15.3.1
15.3.1.1
15.3.1.2
15.3.1.3
15.3.1.4
15.3.1.5
15.3.1.6
Communication is started when communication mode is selected by using the I
I
bus 0 slave address register, and “1” is written to the I20ST bit of the I2C bus 0 control register (I2C0CON).
When “1” is written to the I20ST bit of the I
I20ST bit is “0”), communication is started and the start condition waveform is output to the SDA and SCL pins.
After execution of the start condition, the LSI shifts to slave address transmit mode.
When “1” is written to the I20RS and I20ST bits of the I
(the I20ST bit is “1”), the repeated start condition waveform is output to the SDA and SCL pins. If the communication
is still wished on the bus, it can generate a repeated START condition, address another slave and reverse the
transmit/receive without first generating a STOP condition (see Figure 15-4 Operation Timing at Data
Transmit/Receive Mode (Write/Read) Switching).
After execution of the repeated start condition, the LSI shifts to slave address transmit mode.
In slave address transmit mode, the values (slave address and data communication direction) of the I
address register (I2C0SA) are transmitted in MSB first, and finally, the acknowledgment signal is received in the
I20ACR bit of the I
and I20ACR bit becomes "1" after acknowledgement "1" is received.
At completion of acknowledgment reception, the LSI shifts to the I
state (control register setting wait state).
The value of I2C0SA output from the SDA pin is stored in I2C0RD when the LSI shifts to the I
(I2C0CON) setting wait state (control register setting wait state).
In data transmit mode, the value of I2C0TD is transmitted in MSB first, and finally, the acknowledgment signal is
received in the I20ACR bit of the I
acknowledgement "0" is received and I20ACR bit becomes "1" after acknowledgement "1" is received.
At completion of acknowledgment reception, the LSI shifts to the I
state (control register setting wait state).
The value of I2C0TD output from the SDA pin is stored in I2C0RD.
In data receive mode, the value input in the SDA pin is received synchronously with the rising edge of the serial clock
output to the SCL pin, and finally, the value of the I20ACT bit of the I2C bus 0 control register (I2C0CON) is output as
a acknowledgement. For example, as shown on Figure 15-3 and Figure 15-4, after I20ACT bit is set to "0" (I2CON =
"01H"), acknowledgement "0" ("A" acknowledgement transfer on the Figures) is output And after I20ACT bit is set to
"1" (I2CON = "81H"), acknowledgement "1" ("A" non-acknowledgement transfer on the Figures) is output.
At completion of acknowledgment transmission, the LSI shifts to the I
state (control register setting wait state).
The data received is stored in I2C0RD after the acknowledgment signal is output. The acknowledgment signal output
is received in the I20ACR bit of the I
When the LSI shifts to the control register setting wait state, an I
In the control register setting wait state, the transmit flag (I20ER) of the I
acknowledgment receive data (I20ACR) are confirmed and at data reception, the contents of I2C0RD are read in the
CPU and the next operation mode is selected.
2
C function is enabled by using the I20EN bit, a slave address and a data communication direction are set in the I
Communication Operating Mode
Start Condition
Repeated Start Condition
Slave Address Transmit Mode
Data Transmit Mode
Data Receive Mode
Control Register Setting Wait State
2
C bus 0 status register (I2CSTAT). I20ACR bit becomes "0" after acknowledgement "0" is received
2
C bus 0 status register (I2CSTAT).
2
C bus 0 status register (I2CSTAT). I20ACR bit becomes "0" after
2
C bus 0 control register ((I2C0CON) while communication is stopped (the
15 – 9
2
ML610Q411/ML610Q412/ML610Q415 User’s Manual
C bus 0 control register ((I2C0CON) during communication
2
C bus interface interrupt (I2C0INT) is generated.
2
2
C bus 0 control register (I2C0CON) setting wait
C bus 0 control register (I2C0CON) setting wait
2
C bus 0 control register (I2C0CON) setting wait
2
C bus 0 status register (I2C0STAT) and
2
C bus 0 mode register (I2C0MOD), the
Chapter 15 I
2
C bus 0 control register
2
C Bus Interface
2
C bus 0 slave
2
C