ML610Q412P-NNNTB03A7 Rohm Semiconductor, ML610Q412P-NNNTB03A7 Datasheet - Page 84
ML610Q412P-NNNTB03A7
Manufacturer Part Number
ML610Q412P-NNNTB03A7
Description
MCU 8BIT 16K FLASH 120-TQFP
Manufacturer
Rohm Semiconductor
Datasheets
1.ML610Q482P-NNNTB03A7.pdf
(20 pages)
2.ML610Q411P-NNNTB03A7.pdf
(36 pages)
3.ML610Q411P-NNNTB03A7.pdf
(381 pages)
Specifications of ML610Q412P-NNNTB03A7
Core Processor
nX-U8/100
Core Size
8-Bit
Speed
625kHz
Connectivity
I²C, SSP, UART/USART
Peripherals
LCD, POR, PWM, WDT
Number Of I /o
14
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 2x12b, 2x24b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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5.3.5
Even if the interrupt conditions are satisfied, an interrupt may not be accepted depending on the operating state. This is
called an interrupt disabled state. See below for the interrupt disabled state and the handling of interrupts in this state.
Interrupt disabled state 1:
Interrupt disabled state 2:
Reference:
For the DSR prefix instruction, see “nX-U8/100 Core Instruction Manual”.
When the interrupt conditions are satisfied in this section, an interrupt is generated immediately following the
execution of the instruction at the beginning of the interrupt routine corresponding to the interrupt that has already
been enabled.
When the interrupt conditions are satisfied in this section, an interrupt is generated immediately after execution of
the instruction following the DSR prefix instruction.
Interrupt Disable State
Between the interrupt shift cycle and the instruction at the beginning of the interrupt
routine
Between the DSR prefix instruction and the next instruction
5 – 23
ML610Q411/ML610Q412/ML610Q415 User’s Manual
Chapter 5 Interrupts (INTs)
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