ML610Q412P-NNNTB03A7 Rohm Semiconductor, ML610Q412P-NNNTB03A7 Datasheet - Page 76

• Manufacturer Part Number: ML610Q412P-NNNTB03A7
• Description: MCU 8BIT 16K FLASH 120-TQFP
• Manufacturer: Rohm Semiconductor

Specifications of ML610Q412P-NNNTB03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 625kHz
• Connectivity: I²C, SSP, UART/USART
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 2x12b, 2x24b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.2.14
• QTM2 (bit 5)
• QTM3 (bit 6)
Address: 0F01DH
Access: R/W
Access size: 8 bits
Initial value: 00H
IRQ5 is a special function register (SFR) to request an interrupt for each interrupt source.
Each IRQ5 request flag is set to “1” regardless of the IE5 and MIE values when an interrupt is generated. In this case,
an interrupt is requested to the CPU when the related flag of the interrupt enable register (IE5) is set to “1” and the
master interrupt enable flag (MIE) is set to “1”.
By setting the IRQ5 request flag to “1” by software, an interrupt can be generated.
The corresponding flag of IRQ5 is set to “0” by hardware when the interrupt request is accepted by the CPU.
[Description of Bits]
Note:
When an interrupt is generated by the write instruction to the interrupt request register (IRQ5) or to the interrupt enable
register (IE5), the interrupt shift cycle starts after the next 1 instruction is executed.
Initial value
QTM2 is the request flag for the timer 2 interrupt (TM2INT).
QTM3 is the request flag for the timer 3 interrupt (TM3INT).
IRQ5
R/W
QTM2
QTM3
0
1
0
1
Interrupt Request Register 5 (IRQ5)
No request (initial value)
Request
No request (initial value)
Request
R/W

7
0
QTM3
R/W
6
0
QTM2
R/W
5
0
Description
Description
R/W

5 – 15
0
4
ML610Q411/ML610Q412/ML610Q415 User’s Manual
R/W

3
0
R/W

2
0
Chapter 5 Interrupts (INTs)
R/W

1
0
R/W

0
0