ML610Q412P-NNNTB03A7 Rohm Semiconductor, ML610Q412P-NNNTB03A7 Datasheet - Page 90

• Manufacturer Part Number: ML610Q412P-NNNTB03A7
• Description: MCU 8BIT 16K FLASH 120-TQFP
• Manufacturer: Rohm Semiconductor

Specifications of ML610Q412P-NNNTB03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 625kHz
• Connectivity: I²C, SSP, UART/USART
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 2x12b, 2x24b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.2.3
• SYSCLK (bit 0)
• ENOSC (bit 1)
• ENMLT (bit 2)
Address: 0F003H
Access: R/W
Access size: 8 bits
Initial value: 03H
FCON1 is a special function register (SFR) to control the high-speed clock generation circuit and to select system
clock.
[Description of Bits]
Initial value
The SYSCLK bit is used to select system clock. It allows selection of the low-speed clock (LSCLK) or HSCLK
(1/nOSCLK: n = 1, 2, 4, 8) selected by using the high-speed clock frequency select bit (SYSC1, 0) of FCON0.
When the oscillation of high-speed clock is stopped (ENOSC bit = “0”), the SYSCLK bit is fixed to “0” and the
low-speed clock (LSCLK) is selected for system clock.
The system clock is fixed to HSCLK and this bit always returns “1” when reading on ML610Q415.
The ENOSC bit is used to select enable/disable of the oscillation of the high-speed clock oscillator.
The oscillation of high-speed clock is always enable exept for STOP mode and this bit always returns “1” when
reading on ML610Q415.
The ENMLT bit is used to select enable/disable of the operation of the 2× low-speed clock (LSCLK×2).
FCON1
SYSCLK
R/W
ENOSC
ENMLT
0
1
0
1
0
1
Frequency Control Register 1 (FCON1)
LSCLK
HSCLK (initial value)
Disables high-speed oscillation
Enables high-speed oscillation (initial value)
Disables 2× low-speed clock operation (initial value)
Enables 2× low-speed clock operation

R
7
0
R/W

6
0
R/W

5
0
Description
Description
Description
R/W

0
4
6 – 5
ML610Q411/ML610Q412/ML610Q415 User’s Manual
R/W

3
0
ENMLT
Chapter 6 Clock Generation Circuit
R/W
2
0
ENOSC
R/W
1
1
SYSCLK
R/W
0
1