ML610Q412P-NNNTB03A7 Rohm Semiconductor, ML610Q412P-NNNTB03A7 Datasheet - Page 301

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ML610Q412P-NNNTB03A7

Manufacturer Part Number
ML610Q412P-NNNTB03A7
Description
MCU 8BIT 16K FLASH 120-TQFP
Manufacturer
Rohm Semiconductor

Specifications of ML610Q412P-NNNTB03A7

Core Processor
nX-U8/100
Core Size
8-Bit
Speed
625kHz
Connectivity
I²C, SSP, UART/USART
Peripherals
LCD, POR, PWM, WDT
Number Of I /o
14
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 2x12b, 2x24b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Counter A starts counting of the base clock (BSCLK) when RARUN is set to “1” and the RCON signal (signal
synchronized with the fall of the base clock) is set to “1”.
automatically reset to “0” (6) and counting is terminated. At the same time, an RC-ADC interrupt request (RADIN)
occurs (7).
When the RCON signal is set to “1”, the RC oscillator circuit starts operation and Counter B starts counting of the RC
oscillator clock (RCCLK). When the RARUN bit is reset to “0” due to overflow of Counter A, RC oscillation stops
and Counter B stops counting.
The final count value “nB0” of Counter B is the RCCLK count value during the gate time “nA0 t
expressed by the following expression:
where t
RC oscillation frequency f
CR oscillator circuit
BSCLK
Input waveform
Counter A
Counter B
indicates the BSCLK period and t
nB0
RADINT
RARUN
BSCLK
IN0/IN1
RCCLK
RCON
(1000000H – nA0)
Figure 24-6 Operation Timing in Counter A Reference Mode
RCCLK
000000H
nA0•
t
BSCLK
.
t
RCCLK
t
t
(+1)
BSCLK
RCCLK
000001H 000002H
RCCLK
(+2)
nA0: Reference count value
nB0: Measurement count value
the RCCLK period. That is, “nB0” is a value proportional to the
f
nA0·t
RCCLK
(+3)
24 – 12
ML610Q411/ML610Q412/ML610Q415 User’s Manual
nB0·t
Gate time
BSCLK
RCCLK
Chapter 24 RC Oscillation Type A/D Converter
0FFFFFCH
When Counter A overflows, the RARUN bit is
0FFFFFDH 0FFFFFEH 0FFFFFFH
nB0 – 2
nB0 – 1
(Interrupt request)
nB0
Overflow
000000H
BSCLK
” and is

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