ML610Q412P-NNNTB03A7 Rohm Semiconductor, ML610Q412P-NNNTB03A7 Datasheet - Page 147
ML610Q412P-NNNTB03A7
Manufacturer Part Number
ML610Q412P-NNNTB03A7
Description
MCU 8BIT 16K FLASH 120-TQFP
Manufacturer
Rohm Semiconductor
Datasheets
1.ML610Q482P-NNNTB03A7.pdf
(20 pages)
2.ML610Q411P-NNNTB03A7.pdf
(36 pages)
3.ML610Q411P-NNNTB03A7.pdf
(381 pages)
Specifications of ML610Q412P-NNNTB03A7
Core Processor
nX-U8/100
Core Size
8-Bit
Speed
625kHz
Connectivity
I²C, SSP, UART/USART
Peripherals
LCD, POR, PWM, WDT
Number Of I /o
14
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 2x12b, 2x24b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number:
ML610Q412P-NNNTB03A7
Manufacturer:
ROHM
Quantity:
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Company:
Part Number:
ML610Q412P-NNNTB03A7
Manufacturer:
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Quantity:
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10.3 Description of Operation
10.3.1
The timer counters (TMnC) are set to an operating state (TnSTAT are set to “1”) on the first falling edge of the timer
clocks (TnCK) that are selected by the Timer 0 to 3 control register 0 (TMnCON0) when the TnRUN bits of timer 0 to
3 control register 1 (TMnCON1) are set to “1” and increment the count value on the 2nd falling.
When the count value of TM0 to TM3C and the timer 0 to 3 data register (TMnD) coincide, timer 0 to 3 interrupt
(TMnINT) occurs on the next timer clock falling edge, TMnC are reset to “00H” and incremental counting continues.
When the TnRUN bits are set to “0”, TMnC stop counting after counting once the falling of the timer clock (TnCK).
Confirm that TMnC has been stopped by checking that the TnSTAT bit of the Timer 0–3 control register 1
(TMnCON1) is “0”. When the TnRUN bits are set to “1” again, TMn restart incremental counting from the previous
values. To initialize TMnC to “00H”, perform write operation in TMnC.
The timer interrupt period (TTMI) is expressed by the following equation.
TMnD:
TnCK:
After the TnRUN bits are set to “1”, timers are synchronized by the timer clock and counting starts so that an error of a
maximum of 1 clock period occurs until the first timer interrupt. The timer interrupt periods from the second time are
constant.
Figure 10-2 shows the operation timing diagram of Timer 0 to 3.
Note:
Even if “0” is written to the TnRUN bits, counting operation continues up to the falling edge (the timer 0 to 3 status
flag (TnSTA) is in a “1” state) of the next timer clock pulse. Therefore, the timer 0 to 3 interrupt (TMnINT) may
occur.
Write TMnC
TTMI =
(n = 0 to 3)
Timer mode operation
Timer 0 to 3 data register (TMnD) setting value (01H to 0FFH)
Clock frequency selected by the Timer 0 to 3 control register 0 (TMnCON0)
TnSTAT
TMnINT
TnRUN
TMnC
TMnD
TnCK
XX
TnCK (Hz)
TMnD + 1
Figure 10-2 Operation Timing Diagram of Timer 0 to 3
00
88
(n = 0 to 3)
01
T
TMI
02
10 – 20
ML610Q411/ML610Q412/ML610Q415 User’s Manual
87
88
88
00
01
5F
60
Chapter 10 Timers
88
61
62
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