LFE2M20E-6FN256C LATTICE SEMICONDUCTOR, LFE2M20E-6FN256C Datasheet - Page 101

• Manufacturer Part Number: LFE2M20E-6FN256C
• Description: IC, LATTICEECP2M FPGA, 420MHZ, FPBGA-256
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: LatticeECP2Mr

Specifications of LFE2M20E-6FN256C

• No. Of Logic Blocks: 19000
• No. Of Macrocells: 10500
• No. Of Speed Grades: 6
• No. Of I/o's: 140
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Total Ram Bits: 1217Kbit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Signal Descriptions
April 2008
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
General Purpose
P[Edge] [Row/Column Number*]_[A/B]
GSRN
NC
GND
V
V
V
V
V
XRES
PLLCAP
PLL, DLL and Clock Functions (Used as user programmable I/O pins when not in use for PLL or clock pins)
[LOC][num]_V
[LOC][num]_GPLL[T, C]_IN_A
[LOC][num]_GPLL[T, C]_FB_A
[LOC][num]_SPLL[T, C]_IN_A
[LOC][num]_SPLL[T, C]_FB_A
[LOC][num]_DLL[T, C]_IN_A
[LOC][num]_DLL[T, C]_FB_A
PCLK[T, C]_[n:0]_[3:0]
CC
CCAUX
CCIOx
CCPLL
REF1_x
4
, V
4
REF2_x
Signal Name
CCPLL
I/O
I/O
—
—
—
—
—
—
—
—
—
—
I
I
I
I
I
I
I
I
LatticeECP2/M Family Data Sheet
[Edge] indicates the edge of the device on which the pad is located. Valid
edge designations are L (Left), B (Bottom), R (Right), T (Top).
[Row/Column Number] indicates the PFU row or the column of the device on
which the PIC exists. When Edge is T (Top) or B (Bottom), only need to spec-
ify Row Number. When Edge is L (Left) or R (Right), only need to specify Col-
umn Number.
[A/B] indicates the PIO within the PIC to which the pad is connected. Some of
these user-programmable pins are shared with special function pins. These
pins, when not used as special purpose pins, can be programmed as I/Os for
user logic. During configuration the user-programmable I/Os are tri-stated
with an internal pull-up resistor enabled. If any pin is not used (or not bonded
to a package pin), it is also tri-stated with an internal pull-up resistor enabled
after configuration.
Global RESET signal (active low). Any I/O pin can be GSRN.
No connect.
Ground. Dedicated pins.
Power supply pins for core logic. Dedicated pins.
Auxiliary power supply pin. This dedicated pin powers all the differential and
referenced input buffers.
Dedicated power supply pins for I/O bank x.
PLL supply pins. Should be tied to V
unused.
Reference supply pins for I/O bank x. Pre-determined pins in each bank are
assigned as V
10K ohm +/-1% resistor must be connected between this pad and ground.
External capacitor connection for PLL.
Power supply pin for PLL: ULM, LLM, URM, LRM, num = row from center.
General Purpose PLL (GPLL) input pads: ULM, LLM, URM, LRM, num = row
from center, T = true and C = complement, index A,B,C...at each side.
Optional feedback GPLL input pads: ULM, LLM, URM, LRM, num = row from
center, T = true and C = complement, index A,B,C...at each side.
Secondary PLL (SPLL) input pads: ULM, LLM, URM, LRM, num = row from
center, T = true and C = complement, index A,B,C...at each side.
Optional feedback (SPLL) input pads: ULM, LLM, URM, LRM, num = row
from center, T = true and C = complement, index A,B,C...at each side.
DLL input pads: ULM, LLM, URM, LRM, num = row from center, T = true and
C = complement, index A,B,C...at each side.
Optional feedback (DLL) input pads: ULM, LLM, URM, LRM, num = row from
center, T = true and C = complement, index A,B,C...at each side.
Primary Clock pads, T = true and C = complement, n per side, indexed by
bank and 0,1,2,3 within bank.
4-1
REF
inputs. When not used, they may be used as I/O pins.
Description
Pinout Information
CC
even when the corresponding PLL is
DS1006
Pinout Information_01.8
Data Sheet DS1006