LFE2M20E-6FN256C LATTICE SEMICONDUCTOR, LFE2M20E-6FN256C Datasheet - Page 41

• Manufacturer Part Number: LFE2M20E-6FN256C
• Description: IC, LATTICEECP2M FPGA, 420MHZ, FPBGA-256
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: LatticeECP2Mr

Specifications of LFE2M20E-6FN256C

• No. Of Logic Blocks: 19000
• No. Of Macrocells: 10500
• No. Of Speed Grades: 6
• No. Of I/o's: 140
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Total Ram Bits: 1217Kbit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-36. DQS Local Bus
Polarity Control Logic
In a typical DDR Memory interface design, the phase relationship between the incoming delayed DQS strobe and
the internal system clock (during the READ cycle) is unknown.
The LatticeECP2/M family contains dedicated circuits to transfer data between these domains. To prevent set-up
and hold violations, at the domain transfer between DQS (delayed) and the system clock, a clock polarity selector
is used. This changes the edge on which the data is registered in the synchronizing registers in the input register
block. This requires evaluation at the start of each READ cycle for the correct clock polarity.
Prior to the READ operation in DDR memories, DQS is in tristate (pulled by termination). The DDR memory device
drives DQS low at the start of the preamble state. A dedicated circuit detects the first DQS rising edge after the pre-
amble state. This signal is used to control the polarity of the clock to the synchronizing registers.
*DQSXFERDEL shifts ECLK1 by 90% and is not associated with a particular PIO.
DQSXFER
DQS
DQS
DCNTL[6:0]
ECLK1
DQSXFER
DCNTL[6:0]
CLK1
GSR
DQS
CEI
2-38
DQSXFERDEL*
Polarity Control
DQSDEL
Logic
PIO
PIO
To DDR
Register Block
Register Block
Reg.
Output
Input
Calibration bus
To Sync
LatticeECP2/M Family Data Sheet
from DLL
Reg.
Buffer
Buffer
sysIO
sysIO
DI
DI
Strobe
Datain
DDR
DQS
PAD
PAD
Architecture