LFE2M20E-6FN256C LATTICE SEMICONDUCTOR, LFE2M20E-6FN256C Datasheet - Page 6

• Manufacturer Part Number: LFE2M20E-6FN256C
• Description: IC, LATTICEECP2M FPGA, 420MHZ, FPBGA-256
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: LatticeECP2Mr

Specifications of LFE2M20E-6FN256C

• No. Of Logic Blocks: 19000
• No. Of Macrocells: 10500
• No. Of Speed Grades: 6
• No. Of I/o's: 140
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Total Ram Bits: 1217Kbit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
PFU Blocks
The core of the LatticeECP2/M device consists of PFU blocks, which are provided in two forms, the PFU and PFF.
The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF
blocks can be programmed to perform Logic, Arithmetic and ROM functions. Except where necessary, the remain-
der of this data sheet will use the term PFU to refer to both PFU and PFF blocks.
Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-3. All the interconnec-
tions to and from PFU blocks are from routing. There are 50 inputs and 23 outputs associated with each PFU block.
Figure 2-3. PFU Diagram
Slice
Slice 0 through Slice 2 contain two LUT4s feeding two registers, whereas Slice 3 contains two LUT4s only. For
PFUs, Slice 0 and Slice 2 can also be configured as distributed memory, a capability not available in the PFF.
Table 2-1 shows the capability of the slices in both PFF and PFU blocks along with the operation modes they
enable. In addition, each PFU contains some logic that allows the LUTs to be combined to perform functions such
as LUT5, LUT6, LUT7 and LUT8. There is control logic to perform set/reset functions (programmable as synchro-
nous/asynchronous), clock select, chip-select and wider RAM/ROM functions. Figure 2-4 shows an overview of the
internal logic of the slice. The registers in the slice can be configured for positive/negative and edge triggered or
level sensitive clocks.
Table 2-1. Resources and Modes Available per Slice
Slices 0, 1 and 2 have 14 input signals: 13 signals from routing and one from the carry-chain (from the adjacent
slice or PFU). There are seven outputs: six to routing and one to carry-chain (to the adjacent PFU). Slice 3 has 13
input signals from routing and four signals to routing. Table 2-2 lists the signals associated with Slice 0 to Slice 2.
Slice 0
Slice 1
Slice 2
Slice 3
Slice
2 LUT4s and 2 Registers
2 LUT4s and 2 Registers
2 LUT4s and 2 Registers
FF
LUT4 &
CARRY
D
Slice 0
Resources
2 LUT4s
FF
LUT4 &
CARRY
D
PFU BLock
FF
Logic, Ripple, RAM, ROM
Logic, Ripple, RAM, ROM
LUT4 &
CARRY
D
Logic, Ripple, ROM
Slice 1
Logic, ROM
Modes
LUT4 &
CARRY
FF
D
Routing
Routing
From
2-3
To
FF
CARRY
LUT4 &
D
2 LUT4s and 2 Registers
2 LUT4s and 2 Registers
2 LUT4s and 2 Registers
Slice 2
Resources
LatticeECP2/M Family Data Sheet
FF
CARRY
2 LUT4s
LUT4 &
D
PFF Block
LUT4
Slice 3
Logic, Ripple, ROM
Logic, Ripple, ROM
Logic, Ripple, ROM
LUT4
Logic, ROM
Architecture
Modes