LFE2M20E-6FN256C LATTICE SEMICONDUCTOR, LFE2M20E-6FN256C Datasheet - Page 92

• Manufacturer Part Number: LFE2M20E-6FN256C
• Description: IC, LATTICEECP2M FPGA, 420MHZ, FPBGA-256
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: LatticeECP2Mr

Specifications of LFE2M20E-6FN256C

• No. Of Logic Blocks: 19000
• No. Of Macrocells: 10500
• No. Of Speed Grades: 6
• No. Of I/o's: 140
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Total Ram Bits: 1217Kbit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
SERDES External Reference Clock (LatticeECP2M Family Only)
The external reference clock selection and its interface are a critical part of system applications for this product.
Table 3-13 specifies reference clock requirements, over the full range of operating conditions.
Table 3-13. External Reference Clock Specification (refclkp/refclkn)
Figure 3-13. Jitter Transfer
SERDES Power-Down/Power-Up Specification
Table 3-14. Power-Down and Power-Up Specification
F
F
V
V
V
V
D
T
T
Z
C
1. The signal swing for a single-ended input clock must be as large as the p-p differential swing of a differential input clock to get the same
2. When AC coupled, the input common mode range is determined by:
3. Measured at 50% amplitude.
4. Input capacitance of 1.5pF is total capacitance, including both device and package.
t
t
PWRDN
PWRUP
REF
REF-PPM
REF-R
REF-F
REF-IN-TERM
REF-IN-SE
REF-IN
REF-CM-DC
REF-CM-AC
REF
REF-IN-CAP
gain at the input receiver. Lower swings for the clock may be possible, but will tend to increase jitter.
(Min input level) + (Peak-to-peak input swing)/2 ≤ (Input common mode voltage) ≤ (Max input level) - (Peak-to-peak input swing)/2
Symbol
Symbol
Frequency range
Frequency tolerance
Input swing, single-ended clock
Input levels
Input common mode range (DC coupled)
Input common mode range (AC coupled)
Duty cycle
Rise time (20% to 80%)
Fall time (80% to 20%)
Input termination
Input capacitance
-10.00
-15.00
-20.00
-25.00
-5.00
5.00
0.00
Power-down time after all power down register bits set to ‘0’
Power-up time after all power down register bits set to ‘1’
0.1
Note: This graph is for a nominal device.
3
Description
4
1
Frequency (MHz)
1
Description
2
3-41
Min.
-300
10
100
0.5
25
40
—
0
0
50/2K
DC and Switching Characteristics
Typ.
LatticeECP2/M Family Data Sheet
500
500
—
—
—
—
—
—
—
—
100
V
CCP
Jitter T.
Gain@25°C,1.20V,
PJ=100ps
Max.
1200
1000
1000
320
300
1.2
1.5
1.5
60
+ 0.8
Max.
10
5
mV, p-p
Ohms
Units
MHz
ppm
pF
ps
ps
%
V
V
V
Units
ms
s