LFE2M20E-6FN256C LATTICE SEMICONDUCTOR, LFE2M20E-6FN256C Datasheet - Page 383

• Manufacturer Part Number: LFE2M20E-6FN256C
• Description: IC, LATTICEECP2M FPGA, 420MHZ, FPBGA-256
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: LatticeECP2Mr

Specifications of LFE2M20E-6FN256C

• No. Of Logic Blocks: 19000
• No. Of Macrocells: 10500
• No. Of Speed Grades: 6
• No. Of I/o's: 140
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Total Ram Bits: 1217Kbit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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June 2008
February 2006
August 2006
Date
Version
01.0
01.1
Pinout Information
DC and Switching
Characteristics
Introduction
Architecture
Section
—
LatticeECP2/M Family Data Sheet
Initial release.
Updated Table 1-1 “LatticeECP2 Family Selection Guide”
Updated figure 2-2 “PFU Diagram”
Updated figure 2-13 “Secondary Clock Regions ECP2-50”
Updated figure 2-25 “PIC Diagram”
Updated figure 2-26 “Input Register Block for Left, Right and Bottom
Edges”
Updated figure 2-28 “Output Register Block for Left, Right and Bottom
Edges”
Updated figure 2-30 “DQS Input Routing for Left and Right Edges”
Updated figure 2-32 “Edge Clock, DLL Calibration and DQS Local Bus
Distribution”
Table 2-15 Selectable Master clock (CCLK) frequencies Removed fre-
quencies 15,20,21,22,23,30,34,41,45,51,55,60
Replaced “CLKINDEL” with “CLKO”
Updated SED section
Qualified device migration capability when using DQS banks for DDR
interfaces
Added VCCPLL to the Recommended Operating Conditions Table
Remove Note 5 from “Hot Specifications” section
Added note 7 & 8 to “Initialization Supply current Table
Change Note 6 - “...down to 95MHz” to “...down to 95MHz for DDR and
133MHz for DDR2”
New “Typical Building Block Function Performance” numbers
New External Switching Characteristics numbers
New Internal Switching Characteristics numbers
New Family Timing Adders numbers
Updated Timings for GPLLs, SPLLs and DLLs
Added sysConfig waveforms.
Remove HSTL15D_II from sysIO Recommended Operating Condition
Table
Updated Supply and initialization currents for ECP2-50
Added VCCPLL to the Signal Descriptions Table
Updated Logic signal Connections tables to include 484-fpBGA for the
ECP2-50.
Added Logic signal Connections tables for ECP2-12 devices.
Updated Pin Information Summary table to include ECP2-12.
Updated Power Supply and NC Connections table to include ECP2-12.
Added Note 2 to DDR Strobe (DQS) Pin Table
Added Information on: PCI, DDR & SPI4.2 Capabilities of the device-
Package combination
7-1
Change Summary
Revision History
DS1006 Revision History
Data Sheet DS1006