LFE2M20E-6FN256C LATTICE SEMICONDUCTOR, LFE2M20E-6FN256C Datasheet - Page 146

• Manufacturer Part Number: LFE2M20E-6FN256C
• Description: IC, LATTICEECP2M FPGA, 420MHZ, FPBGA-256
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: LatticeECP2Mr

Specifications of LFE2M20E-6FN256C

• No. Of Logic Blocks: 19000
• No. Of Macrocells: 10500
• No. Of Speed Grades: 6
• No. Of I/o's: 140
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Total Ram Bits: 1217Kbit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
LFE2-20E/SE Logic Signal Connections: 256 fpBGA (Cont.)
* Supports true LVDS. Other differential signals must be emulated with external resistors.
** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.
Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the
last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one
connection with a package ball or pin.
Number
Ball
M15
A16
B12
E15
H14
R12
T15
T16
M3
G5
M2
P5
K5
E3
A1
B5
C8
E2
H8
H9
P9
R5
J3
J8
J9
T1
Ball Number
M15
A16
B12
E15
H14
R12
T15
T16
M3
M2
G5
C8
H8
H9
R5
P5
K5
E3
A1
B5
E2
P9
T1
J3
J8
J9
Ball/Pad Function
VCCIO5
VCCIO6
VCCIO6
VCCIO7
VCCIO7
VCCIO8
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
LFE2-20E/SE
4-46
Bank
5
6
6
7
7
8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LatticeECP2/M Family Data Sheet
Dual Function
Pinout Information
Differential