LFE2M20E-6FN256C LATTICE SEMICONDUCTOR, LFE2M20E-6FN256C Datasheet - Page 25

• Manufacturer Part Number: LFE2M20E-6FN256C
• Description: IC, LATTICEECP2M FPGA, 420MHZ, FPBGA-256
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: LatticeECP2Mr

Specifications of LFE2M20E-6FN256C

• No. Of Logic Blocks: 19000
• No. Of Macrocells: 10500
• No. Of Speed Grades: 6
• No. Of I/o's: 140
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Total Ram Bits: 1217Kbit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 2-7. Maximum Number of Elements in a Block
Some options are available in four elements. The input register in all the elements can be directly loaded or can be
loaded as a shift register from previous operand registers. By selecting “dynamic operation” the following opera-
tions are possible:
• In the ‘Signed/Unsigned’ options the operands can be switched between signed and unsigned on every cycle.
• In the ‘Add/Sub’ option the Accumulator can be switched between addition and subtraction on every cycle.
• The loading of operands can switch between parallel and serial operations.
MULT sysDSP Element
This multiplier element implements a multiply with no addition or accumulator nodes. The two operands, A and B,
are multiplied and the result is available at the output. The user can enable the input/output and pipeline registers.
Figure 2-23 shows the MULT sysDSP element.
Figure 2-23. MULT sysDSP Element
MULT
MAC
MULTADDSUB
MULTADDSUBSUM
Width of Multiply
Multiplicand
Multiplier
Signed A
Signed B
Shift Register B Out
Shift Register B In
n
Register B
Input Data
n
n
n
Register
Register
Input
Input
x9
8
2
4
2
m
Register A
Input Data
m
m
Shift Register A Out
m
Shift Register A In
2-22
Multiplier
Multiplier
m
n
To
To
Multiplier
Register
Pipeline
x
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
x18
4
2
2
1
LatticeECP2/M Family Data Sheet
(default)
m+n
m+n
Output
Architecture
x36
—
—
—
1