LFE2M20E-6FN256C LATTICE SEMICONDUCTOR, LFE2M20E-6FN256C Datasheet - Page 79

• Manufacturer Part Number: LFE2M20E-6FN256C
• Description: IC, LATTICEECP2M FPGA, 420MHZ, FPBGA-256
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: LatticeECP2Mr

Specifications of LFE2M20E-6FN256C

• No. Of Logic Blocks: 19000
• No. Of Macrocells: 10500
• No. Of Speed Grades: 6
• No. Of I/o's: 140
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Total Ram Bits: 1217Kbit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
LatticeECP2/M Internal Switching Characteristics
PFU/PFF Logic Mode Timing
t
t
t
t
t
t
t
t
PFU Dual Port Memory Mode Timing
t
t
t
t
t
t
t
PIC Timing
PIO Input/Output Buffer Timing
t
t
IOLOGIC Input/Output Timing
t
t
t
t
t
t
t
EBR Timing
t
t
t
t
t
t
t
LUT4_PFU
LUT6_PFU
LSR_PFU
SUM_PFU
HM_PFU
SUD_PFU
HD_PFU
CK2Q_PFU
CORAM_PFU
SUDATA_PFU
HDATA_PFU
SUADDR_PFU
HADDR_PFU
SUWREN_PFU
HWREN_PFU
IN_PIO
OUT_PIO
SUI_PIO
HI_PIO
COO_PIO
SUCE_PIO
HCE_PIO
SULSR_PIO
HLSR_PIO
CO_EBR
COO_EBR
SUDATA_EBR
HDATA_EBR
SUADDR_EBR
HADDR_EBR
SUWREN_EBR
Parameter
LUT4 delay (A to D inputs to F output)
LUT6 delay (A to D inputs to OFX output)
Set/Reset to output of PFU (Asynchro-
nous)
Clock to Mux (M0,M1) Input Setup Time
Clock to Mux (M0,M1) Input Hold Time
Clock to D input setup time
Clock to D input hold time
Clock to Q delay, (D-type Register Configu-
ration)
Clock to Output (F Port)
Data Setup Time
Data Hold Time
Address Setup Time
Address Hold Time
Write/Read Enable Setup Time
Write/Read Enable Hold Time
Input Buffer Delay (LVCMOS25)
Output Buffer Delay (LVCMOS25)
Input Register Setup Time (Data Before
Clock)
Input Register Hold Time (Data after
Clock)
Output Register Clock to Output Delay
Input Register Clock Enable Setup Time
Input Register Clock Enable Hold Time
Set/Reset Setup Time
Set/Reset Hold Time
Clock (Read) to output from Address or
Data
Clock (Write) to output from EBR output
Register
Setup Data to EBR Memory
Hold Data to EBR Memory
Setup Address to EBR Memory
Hold Address to EBR Memory
Setup Write/Read Enable to PFU Memory
Description
Over Recommended Operating Conditions
3-28
-0.051
-0.172
-0.245
-0.122
-0.570
-0.022
-0.080
-0.157
-0.115
-0.128
0.061
0.002
0.199
0.246
0.132
0.596
0.184
0.173
0.138
0.128
0.032
Min.
—
—
—
—
—
—
—
—
—
—
-7
0.180
0.304
0.600
0.285
0.902
0.613
1.115
Max.
0.61
2.51
0.33
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
1
-0.049
-0.205
-0.284
-0.145
-0.614
-0.025
-0.086
-0.181
-0.130
-0.149
0.129
0.071
0.003
0.235
0.285
0.156
0.645
0.037
0.201
0.195
0.155
Min.
—
—
—
—
—
—
—
—
—
—
-6
0.198
0.331
0.655
0.309
1.083
0.681
1.115
Max.
0.66
2.75
0.36
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-0.046
-0.238
-0.323
-0.168
-0.658
-0.028
-0.093
-0.205
-0.145
-0.170
0.129
0.081
0.003
0.271
0.324
0.180
0.694
0.041
0.217
0.217
0.172
Min.
—
—
—
—
—
—
—
—
—
—
-5
0.216
0.358
0.711
0.333
1.263
0.749
1.343
Max.
0.72
2.99
0.39
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns