LFE2M20E-6FN256C LATTICE SEMICONDUCTOR, LFE2M20E-6FN256C Datasheet - Page 266

• Manufacturer Part Number: LFE2M20E-6FN256C
• Description: IC, LATTICEECP2M FPGA, 420MHZ, FPBGA-256
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: LatticeECP2Mr

Specifications of LFE2M20E-6FN256C

• No. Of Logic Blocks: 19000
• No. Of Macrocells: 10500
• No. Of Speed Grades: 6
• No. Of I/o's: 140
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Total Ram Bits: 1217Kbit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
LFE2M50E/SE Logic Signal Connections: 484 fpBGA (Cont.)
* Supports true LVDS. Other differential signals must be emulated with external resistors.
** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.
***For density migration, board design must take into account that these sysCONFIG pins are dual function for the lower density devices
(ECP2M20 and ECP2M35) and are dedicated pins for the higher density devices (ECP2M50, ECP2M70 and ECP2M100).
****Due to packaging bond out option, this DQS does not have all the necessary DQ pins bonded out for a full 8-bit data width.
Note: VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the
last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one
connection with a package ball or pin.
Ball Number
W19
W18
G14
G15
G12
G13
V17
V18
D15
D14
E15
E14
H15
R15
F15
F14
F13
H8
R8
Ball/Pad Function
VCCPLL
VCCPLL
VCCPLL
VCCPLL
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
LFE2M50E/SE
4-166
Bank
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LatticeECP2/M Family Data Sheet
Dual Function
Pinout Information
Differential