LFE2M20E-6FN256C LATTICE SEMICONDUCTOR, LFE2M20E-6FN256C Datasheet - Page 295

• Manufacturer Part Number: LFE2M20E-6FN256C
• Description: IC, LATTICEECP2M FPGA, 420MHZ, FPBGA-256
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: LatticeECP2Mr

Specifications of LFE2M20E-6FN256C

• No. Of Logic Blocks: 19000
• No. Of Macrocells: 10500
• No. Of Speed Grades: 6
• No. Of I/o's: 140
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Total Ram Bits: 1217Kbit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA
Lattice Semiconductor
Number
GNDIO
GNDIO
VCCIO
VCCIO
Ball
H23
H24
D28
E28
G24
H25
D27
E27
G25
G23
C30
A29
B30
B29
C27
A26
A27
B26
C26
B25
C25
A25
C29
B28
C28
A28
B24
E24
D24
C24
A20
C20
B20
C19
A23
C23
B23
C22
B22
A21
F26
F24
F25
-
-
URC_SQ_VCCAUX33
URC_SQ_HDOUTN0
URC_SQ_HDOUTN1
URC_SQ_HDOUTN2
URC_SQ_HDOUTN3
URC_SQ_HDOUTP0
URC_SQ_HDOUTP1
URC_SQ_REFCLKN
URC_SQ_HDOUTP2
URC_SQ_REFCLKP
URC_SQ_VCCRX0
URC_SQ_VCCOB0
URC_SQ_VCCOB1
URC_SQ_VCCRX1
URC_SQ_VCCRX2
URC_SQ_VCCOB2
URC_SQ_VCCOB3
URC_SQ_VCCTX0
URC_SQ_VCCTX1
URC_SQ_VCCTX2
URC_SQ_HDINP0
URC_SQ_HDINN0
URC_SQ_HDINN1
URC_SQ_HDINP1
URC_SQ_HDINP2
URC_SQ_HDINN2
URC_SQ_VCCIB0
URC_SQ_VCCIB1
URC_SQ_VCCIB2
URC_SQ_VCCP
Function
Ball/Pad
GNDIO2
GNDIO2
VCCIO2
VCCIO2
PR13B
PR13A
PR12B
PR12A
PR11B
PR11A
PR9B
PR9A
XRES
NC
NC
NC
NC
-
-
LFE2M50E/SE
Bank
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
2
2
2
2
2
2
2
2
2
-
-
-
-
-
-
-
-
-
-
RUM0_SPLLC_FB_A
RUM0_SPLLT_FB_A
RUM0_SPLLC_IN_A
RUM0_SPLLT_IN_A
Dual Function
VREF2_2
VREF1_2
Differential
C (LVDS)*
C (LVDS)*
T (LVDS)*
T (LVDS)*
4-195
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
URC_SQ_VCCAUX33
URC_SQ_HDOUTP0
URC_SQ_HDOUTN0
URC_SQ_HDOUTN1
URC_SQ_HDOUTP1
URC_SQ_HDOUTP2
URC_SQ_HDOUTN2
URC_SQ_HDOUTN3
URC_SQ_REFCLKN
URC_SQ_REFCLKP
URC_SQ_VCCOB0
URC_SQ_VCCOB1
URC_SQ_VCCOB2
URC_SQ_VCCOB3
URC_SQ_VCCRX0
URC_SQ_VCCTX0
URC_SQ_VCCTX1
URC_SQ_VCCRX1
URC_SQ_VCCRX2
URC_SQ_VCCTX2
URC_SQ_HDINP0
URC_SQ_VCCIB0
URC_SQ_HDINN0
URC_SQ_HDINN1
URC_SQ_VCCIB1
URC_SQ_HDINP1
URC_SQ_HDINP2
URC_SQ_VCCIB2
URC_SQ_HDINN2
URC_SQ_VCCP
Function
Ball/Pad
VCCIO2
GNDIO2
VCCIO2
GNDIO2
VCCIO2
PR15B
PR15A
PR14B
PR14A
PR13B
PR13A
PR12B
PR12A
PR11B
PR11A
XRES
PR9B
PR9A
-
LatticeECP2/M Family Data Sheet
Bank
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
-
-
-
LFE2M70E/SE
RUM0_SPLLC_FB_A/RDQ15
RUM0_SPLLT_FB_A/RDQ15
RUM0_SPLLC_IN_A/RDQ15
RUM0_SPLLT_IN_A/RDQ15
Dual Function
Pinout Information
VREF2_2
VREF1_2
RDQS15
RDQ15
RDQ15
RDQ15
RDQ15
RDQ15
Differential
C (LVDS)*
C (LVDS)*
C (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
C
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
T