LFE2M20E-6FN256C LATTICE SEMICONDUCTOR, LFE2M20E-6FN256C Datasheet - Page 52

• Manufacturer Part Number: LFE2M20E-6FN256C
• Description: IC, LATTICEECP2M FPGA, 420MHZ, FPBGA-256
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: LatticeECP2Mr

Specifications of LFE2M20E-6FN256C

• No. Of Logic Blocks: 19000
• No. Of Macrocells: 10500
• No. Of Speed Grades: 6
• No. Of I/o's: 140
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Total Ram Bits: 1217Kbit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Absolute Maximum Ratings
1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. Overshoot and undershoot of -2V to (V
February 2008
Recommended Operating Conditions
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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Supply Voltage V
Supply Voltage V
Supply Voltage V
Output Supply Voltage V
Input or I/O Tristate Voltage Applied
Storage Temperature (Ambient) . . . . . . . . . -65 to 150°C
Junction Temperature (Tj) . . . . . . . . . . . . . . . . . . +125°C
V
V
V
V
V
t
t
SERDES External Power Supply (For LatticeECP2M Family Only)
V
V
V
V
V
V
1. If V
2. See recommended voltages by I/O standard in subsequent table.
3. V
4. For proper power-up configuration, users must ensure that the configuration control signals such as the CFGx, INITN, PROGRAMN and
5. For power-up, V
6. V
JCOM
JIND
CC
CCAUX
CCPLL
CCIO
CCJ
CCIB
CCOB
CCAUX33
CCRX
CCTX
CCP
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
nected to the same power supply as V
DONE pins are driven to the proper logic levels when the device powers up. The device power-up is triggered by the last of V
V
(configuration I/O bank) voltage must be powered up prior to or at the same time as the last of VCC or VCCAUX reaches its minimum levels.
CCAUX
CCIO8
CCRX
1, 4, 5
1
6
CCIO
1, 2, 4
6
6
1, 3, 4, 5
Symbol
,V
supplies that reaches its minimum valid levels. Alternatively, if the configuration control signals are pulled up by V
ramp rate must not exceed 30mV/µs during power-up when transitioning between 0V and 3.3V.
or V
CCTX
CCJ
and V
CC
is set to 1.2V, they must be connected to the same power supply as V
CC
CCAUX
CCJ
must reach its valid minimum value before powering up V
CCP
. . . . . . . . . . . . . . . . . . . -0.5 to 1.32V
. . . . . . . . . . . . . . . . . . -0.5 to 3.75V
must be tied together in each quad and all quads need to be powered up.
Core Supply Voltage
Auxiliary Supply Voltage
PLL Supply Voltage
I/O Driver Supply Voltage
Supply Voltage for IEEE 1149.1 Test Access Port
Junction Temperature, Commercial Operation
Junction Temperature, Industrial Operation
Input Buffer Power Supply (1.2V)
Input Buffer Power Supply (1.5V)
Output Buffer Power Supply (1.2V)
Output Buffer Power Supply (1.5V)
Termination Resistor Switching Power Supply
Receive Power Supply
Transmit Power Supply
PLL and Reference Clock Buffer Power
. . . . . . . . . . . . . . . . -0.5 to 3.75V
CCIO
. . . . . . . . . . . -0.5 to 3.75V
IHMAX
CCAUX
4
. . . . . . -0.5 to 3.75V
+ 2) volts is permitted for a duration of <20ns.
. V
CC
1, 2, 3
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
and V
CCPLL
Parameter
must be connected to the same power supply.
3-1
CCAUX
(LatticeECP2/M “S” version devices only).
CC.
If V
CCIO
or V
DS1006
CCJ
3.135
1.425
1.425
3.135
Min.
1.14
1.14
1.14
1.14
1.14
1.14
1.14
1.14
1.14
is set to 3.3V, they must be con-
-40
0
DC and Switching_01.7
Data Sheet DS1006
3.465
3.465
3.465
1.575
1.575
3.465
Max.
1.26
1.26
1.26
1.26
1.26
1.26
1.26
100
85
CCIO8
CC
, the V
, V
CCAUX
Units
°C
°C
V
V
V
V
V
V
V
V
V
V
V
V
V
CCIO8
or