LFE2M20E-6FN256C LATTICE SEMICONDUCTOR, LFE2M20E-6FN256C Datasheet - Page 51

• Manufacturer Part Number: LFE2M20E-6FN256C
• Description: IC, LATTICEECP2M FPGA, 420MHZ, FPBGA-256
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: LatticeECP2Mr

Specifications of LFE2M20E-6FN256C

• No. Of Logic Blocks: 19000
• No. Of Macrocells: 10500
• No. Of Speed Grades: 6
• No. Of I/o's: 140
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Total Ram Bits: 1217Kbit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
for checking soft errors (SED) in SRAM. This SED operation can be run in the background during user mode. If a
soft error occurs, during user mode (normal operation) the device can be programmed to either reload from a
known good boot image or generate an error signal.
For further information about Soft Error Detect (SED) support, please see the list of additional technical documen-
tation at the end of this data sheet.
External Resistor
LatticeECP2/M devices require a single external, 10K ohm ±1% value between the XRES pin and ground. Device
configuration will not be completed if this resistor is missing. There is no boundary scan register on the external
resistor pad.
On-Chip Oscillator
Every LatticeECP2/M device has an internal CMOS oscillator which is used to derive a Master Clock for configura-
tion. The oscillator and the Master Clock run continuously and are available to user logic after configuration is com-
pleted. The software default value of the Master Clock is 2.5MHz. Table 2-16 lists all the available Master
Configuration Clock frequencies for normal non-encrypted mode and encrypted mode. When a different Master
Clock is selected during the design process, the following sequence takes place:
1. Device powers up with a Master Clock frequency of 3.1MHz.
2. During configuration, users select a different master clock frequency.
3. The Master Clock frequency changes to the selected frequency once the clock configuration bits are received.
4. If the user does not select a master clock frequency, then the configuration bitstream defaults to the Master
This internal CMOS oscillator is available to the user by routing it as an input clock to the clock tree. For further
information about the use of this oscillator for configuration or user mode, please see the list of additional technical
documentation at the end of this data sheet.
Table 2-16. Selectable Master Clock (CCLK) Frequencies During Configuration
Density Shifting
The LatticeECP2/M family is designed to ensure that different density devices in the same family and in the same
package have the same pinout. Furthermore, the architecture ensures a high success rate when performing design
migration from lower density devices to higher density devices. In many cases, it is also possible to shift a lower uti-
lization design targeted for a high-density device to a lower density device. However, the exact details of the final
resource utilization will impact the likelihood of success in each case. Design migration between LatticeECP2 and
LatticeECP2M families is not possible. For specific requirements relating to sysCONFIG pins of the ECP2M50,
M70 and M100, see the Logic Signal Connections tables.
Clock frequency of 2.5MHz.
1. Software default frequency.
10.0
2.5
4.3
5.4
6.9
8.1
9.2
Non-Encrypted Mode CCLK (MHz)
1
13.0
15.0
20.0
26.0
30.0
34.0
41.0
130.0
2-48
45.0
55.0
60.0
—
—
—
Encrypted Mode CCLK (MHz)
LatticeECP2/M Family Data Sheet
10.0
34.0
41.0
45.0
2.5
5.4
—
1
Architecture