LFE2M20E-6FN256C LATTICE SEMICONDUCTOR, LFE2M20E-6FN256C Datasheet - Page 24

• Manufacturer Part Number: LFE2M20E-6FN256C
• Description: IC, LATTICEECP2M FPGA, 420MHZ, FPBGA-256
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: LatticeECP2Mr

Specifications of LFE2M20E-6FN256C

• No. Of Logic Blocks: 19000
• No. Of Macrocells: 10500
• No. Of Speed Grades: 6
• No. Of I/o's: 140
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Total Ram Bits: 1217Kbit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
(FIR) filters, Fast Fourier Transforms (FFT) functions, Correlators, Reed-Solomon/Turbo/Convolution encoders and
decoders. These complex signal processing functions use similar building blocks such as multiply-adders and mul-
tiply-accumulators.
sysDSP Block Approach Compared to General DSP
Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with
fixed data-width multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased by
higher clock speeds. The LatticeECP2/M, on the other hand, has many DSP blocks that support different data-
widths. This allows the designer to use highly parallel implementations of DSP functions. The designer can opti-
mize the DSP performance vs. area by choosing an appropriate level of parallelism. Figure 2-22 compares the fully
serial and the mixed parallel and serial implementations.
Figure 2-22. Comparison of General DSP and LatticeECP2/M Approaches
sysDSP Block Capabilities
The sysDSP block in the LatticeECP2/M family supports four functional elements in three 9, 18 and 36 data path
widths. The user selects a function element for a DSP block and then selects the width and type (signed/unsigned)
of its operands. The operands in the LatticeECP2/M family sysDSP Blocks can be either signed or unsigned but not
mixed within a function element. Similarly, the operand widths cannot be mixed within a block. In the LatticeECP2/
M family the DSP elements can be concatenated.
The resources in each sysDSP block can be configured to support the following four elements:
• MULT (Multiply)
• MAC (Multiply, Accumulate)
• MULTADDSUB (Multiply, Addition/Subtraction)
• MULTADDSUBSUM (Multiply, Addition/Subtraction, Accumulate)
The number of elements available on each block depends in the width selected from the three available options x9,
x18, and x36. A number of these elements are concatenated for highly parallel implementations of DSP functions.
Table 2-7 shows the capabilities of the block.
Accumulator
Multiplier
Single
Operand
Function implemented in
General purpose DSP
A
x
Operand
B
M loops
Operand
A
x
Operand
Multiplier 0
B
2-21
Multiplier 1
Operand
A
accumulate
Function implemented
x
(k adds)
m/k
in LatticeECP2/M
Operand
B
+ +
LatticeECP2/M Family Data Sheet
Output
Operand
A
x
Operand
Multiplier k
B
loops
m/k
Architecture