LFE2M20E-6FN256C LATTICE SEMICONDUCTOR, LFE2M20E-6FN256C Datasheet - Page 76

• Manufacturer Part Number: LFE2M20E-6FN256C
• Description: IC, LATTICEECP2M FPGA, 420MHZ, FPBGA-256
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: LatticeECP2Mr

Specifications of LFE2M20E-6FN256C

• No. Of Logic Blocks: 19000
• No. Of Macrocells: 10500
• No. Of Speed Grades: 6
• No. Of I/o's: 140
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Total Ram Bits: 1217Kbit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LatticeECP2/M External Switching Characteristics
t
XGMII I/O Pin Parameters (312 Mbps)
t
t
t
t
Primary
f
t
t
Edge Clock
f
t
t
1. General timing numbers based on LVCMOS 2.5, 12mA, 0pf load.
2. DDR timing numbers based on SSTL25 for BGA packages only.
3. DDR2 timing numbers based on SSTL18 for BGA packages only.
4. SPI4.2 and SFI4 timing numbers based on LVDS25 for BGA packages only.
5. XGMII timing numbers based on HSTL class I. A corresponding left/right dedicated clock buffer is used when using the SPI4.2 interface to
6. IP will be used to support DDR and DDR2 memory data rates down to 95MHz. This approach uses a free-running clock and PFU register to
7. Using the LVDS I/O standard.
8. ECP2-6 and ECP2-12 do not support SPI4.2
9. The AC numbers do not apply to PCLK6 and PCLK7.
10. Applies to CLKOP only.
11. Please refer to technical note TN1159, LatticeECP2M Pin Assignment Recommendations for best performance.
Timing v.A 0.11
Lattice Semiconductor
DIBSPI
SUXGMII
HXGMII
DVBCKXGMII
DVACKXGMII
MAX_PRI
W_PRI
SKEW_PRI
MAX_EDGE
W_EDGE
SKEW_EDGE
Parameter
the left or right edge of the device. For SPI4.2 mode, the software tool will help in selecting the appropriate clock buffer.
sample the data instead of the hardwired DDR memory interface.
7
7
Data Invalid Before Clock (Transmit)
Data Setup Before Read Clock
Data Hold After Read Clock
Data Valid Before Clock
Data Valid After Clock
Frequency for Primary Clock Tree
Clock Pulse Width for Primary Clock ECP2/M
Primary Clock Skew Within a Bank
Frequency for Edge Clock
Clock Pulse Width for Edge Clock
Edge Clock Skew Within an Edge of
the Device
Description
Over Recommended Operating Conditions
5
ECP2-20
ECP2-35
ECP2-50
ECP2-70
ECP2M20
ECP2M35
ECP2M50
ECP2M70
ECP2M100
ECP2/M
ECP2/M
ECP2/M
ECP2/M
ECP2/M
ECP2/M
ECP2/M
ECP2/M
ECP2/M
Device
3-25
Min.
0.95
0.95
480
480
960
960
—
—
—
—
—
—
—
—
—
—
—
—
—
-7
Max.
280
280
280
280
230
230
230
230
230
420
300
420
300
—
—
—
—
—
—
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
9
Min.
1.19
1.19
480
480
960
960
(Continued)
—
—
—
—
—
—
—
—
—
—
—
—
—
-6
Max.
280
280
280
280
230
230
230
230
230
357
360
357
360
—
—
—
—
—
—
Min.
2.00
2.00
480
480
960
960
—
—
—
—
—
—
—
—
—
—
—
—
—
-5
Max.
280
280
280
280
230
230
230
230
230
311
420
311
420
—
—
—
—
—
—
Units
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ns
ps
ns
ps