LFE2M20E-6FN256C LATTICE SEMICONDUCTOR, LFE2M20E-6FN256C Datasheet - Page 102

• Manufacturer Part Number: LFE2M20E-6FN256C
• Description: IC, LATTICEECP2M FPGA, 420MHZ, FPBGA-256
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: LatticeECP2Mr

Specifications of LFE2M20E-6FN256C

• No. Of Logic Blocks: 19000
• No. Of Macrocells: 10500
• No. Of Speed Grades: 6
• No. Of I/o's: 140
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Total Ram Bits: 1217Kbit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Signal Descriptions (Cont.)
[LOC]DQS[num]
Test and Programming (Dedicated Pins)
TMS
TCK
TDI
TDO
VCCJ
Configuration Pads (Used During sysCONFIG)
CFG[2:0]
INITN
PROGRAMN
DONE
CCLK
BUSY/SISPI
CSN
CS1N
WRITEN
D[0]/SPIFASTN
D[1:6]
D[7]/SPID0
DOUT/CSON
DI/CSSPI0N
Dedicated SERDES Signals
[LOC]_SQ_VCCAUX33
[LOC]_SQ_REFCLKN
[LOC]_SQ_REFCLKP
[LOC]_SQ_VCCP
[LOC]_SQ_VCCIBm
Signal Name
1, 2, 3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
—
—
—
O
O
I
I
I
I
I
I
I
I
I
I
I
DQS input pads: T (Top), R (Right), B (Bottom), L (Left), DQS, num = ball
function number. Any pad can be configured to be output.
Test Mode Select input, used to control the 1149.1 state machine. Pull-up is
enabled during configuration.
Test Clock input pin, used to clock the 1149.1 state machine. No pull-up
enabled.
Test Data in pin. Used to load data into device using 1149.1 state machine.
After power-up, this TAP port can be activated for configuration by sending
appropriate command. (Note: once a configuration port is selected it is
locked. Another configuration port cannot be selected until the power-up
sequence). Pull-up is enabled during configuration.
Output pin. Test Data Out pin used to shift data out of a device using 1149.1.
Power supply pin for JTAG Test Access Port.
Mode pins used to specify configuration mode values latched on rising edge
of INITN. During configuration, a pull-up is enabled. These are dedicated
pins.
Open Drain pin. Indicates the FPGA is ready to be configured. During config-
uration, a pull-up is enabled. It is a dedicated pin.
Initiates configuration sequence when asserted low. This pin always has an
active pull-up. This is a dedicated pin.
Open Drain pin. Indicates that the configuration sequence is complete, and
the startup sequence is in progress. This is a dedicated pin.
Configuration Clock for configuring an FPGA in sysCONFIG mode.
Read control command in SPI or SPIm mode.
sysCONFIG chip select (active low). During configuration, a pull-up is
enabled.
sysCONFIG chip select (active low). During configuration, a pull-up is
enabled.
Write Data on Parallel port (active low).
sysCONFIG Port Data I/O for Parallel mode.
sysCONFIG Port Data I/O for SPI or SPIm. When using the SPI or SPIm
mode, this pin should either be tied high or low, must not be left floating.
sysCONFIG Port Data I/O for Parallel
sysCONFIG Port Data I/O for Parallel, SPI, SPIm
Output for serial configuration data (rising edge of CCLK) when using
sysCONFIG port.
Input for serial configuration data (clocked with CCLK) when using sysCON-
FIG port. During configuration, a pull-up is enabled. Output when used in SPI/
SPIm modes.
Termination resistor switching power (3.3V). This pin must be tied to 3.3V
even if the quad is unused.
Negative Reference Clock Input
Positive Reference Clock Input
PLL and Reference clock buffer power (1.2V). This pin must be tied to 1.2V
even if the quad is unused.
Input buffer power supply, channel m (1.2V/1.5V). This pin should be left float-
ing if the channel is unused.
4-2
LatticeECP2/M Family Data Sheet
Description
Pinout Information