LFE2M20E-6FN256C LATTICE SEMICONDUCTOR, LFE2M20E-6FN256C Datasheet - Page 13

• Manufacturer Part Number: LFE2M20E-6FN256C
• Description: IC, LATTICEECP2M FPGA, 420MHZ, FPBGA-256
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: LatticeECP2Mr

Specifications of LFE2M20E-6FN256C

• No. Of Logic Blocks: 19000
• No. Of Macrocells: 10500
• No. Of Speed Grades: 6
• No. Of I/o's: 140
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Total Ram Bits: 1217Kbit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
The DLLs in the LatticeECP2/M are used to shift the clock in relation to the data for source synchronous inputs.
PLLs are used for frequency synthesis and clock generation for source synchronous interfaces. Cascading PLL
and DLL blocks allows applications to utilize the unique benefits of both DLLs and PLLs.
For further information about the DLL, please see the list of additional technical documentation at the end of this
data sheet.
GPLL/SPLL/GDLL PIO Input Pin Connections (LatticeECP2M Family Only)
All LatticeECP2M devices contain two GDLLs, two GPLLs and six SPLLs, arranged in quadrants as shown in
Figure 2-8. In the LatticeECP2M devices GPLLs, SPLLs and GDLLs share their input pins. Figure 2-8 shows the
sharing of SPLLs input pin connections in the upper two quadrants and the sharing of GDLL, GPLL and SPLL input
pin connections in the lower two quadrants.
Figure 2-8. Sharing of PIO Pins by GPLL, SPLL and GDLL in LatticeECP2M Devices
Clock Dividers
LatticeECP2/M devices have two clock dividers, one on the left side and one on the right side of the device. These
are intended to generate a slower-speed system clock from a high-speed edge clock. The block operates in a ÷2,
÷4 or ÷8 mode and maintains a known phase relationship between the divided down clock and the high-speed
clock based on the release of its reset signal. The clock dividers can be fed from selected PLL/DLL outputs, DLL-
DELA delay blocks, routing or from an external clock input. The clock divider outputs serve as primary clock
sources and feed into the clock distribution network. The Reset (RST) control signal resets input and synchro-
nously forces all outputs to low. The RELEASE signal releases outputs synchronously to the input clock. For further
information about clock dividers, please see the list of additional technical documentation at the end of this data
sheet. Figure 2-9 shows the clock divider connections.
GPLL_PIO
GDLL_PIO
SPLL_PIO
SPLL_PIO
SPLL_PIO
Upper Left Quadrant
Lower Left Quadrant
GPLL
GDLL
SPLL
SPLL
SPLL
2-10
Upper Right Quadrant
Lower Right Quadrant
GPLL
GDLL
SPLL
SPLL
SPLL
LatticeECP2/M Family Data Sheet
GDLL_PIO
SPLL_PIO
SPLL_PIO
SPLL_PIO
GPLL_PIO
Architecture