MT47H64M16HR-3 IT:H Micron Technology Inc, MT47H64M16HR-3 IT:H Datasheet - Page 103

• Manufacturer Part Number: MT47H64M16HR-3 IT:H
• Description: DRAM Chip DDR2 SDRAM 1G-Bit 64Mx16 1.8V 84-Pin FBGA Tray
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H64M16HR-3 IT:H

• Density: 1 Gb
• Maximum Clock Rate: 667 MHz
• Package: 84FBGA
• Operating Supply Voltage: 1.8 V
• Maximum Random Access Time: 0.45 ns
• Operating Temperature: -40 to 85 °C
• Organization: 64Mx16
• Address Bus: 16b
• Access Time (max): 450ps
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 135mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Figure 55: x16 Data Output Timing –
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. V 6/10 EN
DQ8–DQ15 and UDQS collectively 6
DQ0–DQ7 and LDQS collectively 6
DQ (first data no longer valid) 4
DQ (first data no longer valid) 4
DQ (first data no longer valid) 7
DQ (first data no longer valid) 7
DQ (last data valid) 4
DQ (last data valid) 4
DQ (last data valid) 7
DQ (last data valid) 7
Notes:
UDQS#
UDQS 3
LDSQ#
LDQS 3
1.
2.
3. DQ transitioning after the DQS transitions define the
4. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
DQ 4
DQ 4
DQ 4
DQ 4
DQ 4
DQ 4
DQ 7
DQ 7
DQ 7
DQ 7
DQ 7
DQ 7
CK#
CK
t
t
transitions, and ends with the last valid transition of DQ.
lower byte, and UDQS defines the upper byte.
HP is the lesser of
DQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS
T1
t HP 1
t
DQSQ,
t HP 1
t
CL or
t DQSQ 2
t
t QH 5
QH, and Data Valid Window
t DQSQ 2
T2
t QH 5
Data valid
t
window
103
CH clock transitions collectively when a bank is active.
Data valid
T2
T2
T2
t HP 1
window
T2
T2
T2
t DQSQ 2
t QHS
T2n
t QH 5
t DQSQ 2
t QHS
t QH 5
Data valid
window
t HP 1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T2n
T2n
T2n
Data valid
window
T2n
T2n
T2n
T3
t DQSQ 2
t QHS
t QH 5
1Gb: x4, x8, x16 DDR2 SDRAM
t QHS
t DQSQ 2
t QH 5
t HP 1
Data valid
window
Data valid
window
T3
T3
T3
T3
T3n
T3
T3
t
DQSQ window. LDQS defines the
t DQSQ 2
t DQSQ 2
t QHS
t QHS
t HP 1
t QH 5
t QH 5
Data valid
window
Data valid
© 2004 Micron Technology, Inc. All rights reserved.
window
T3n
T4
T3n
T3n
T3n
T3n
T3n
t QHS
t QHS
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