MT47H64M16HR-3 IT:H Micron Technology Inc, MT47H64M16HR-3 IT:H Datasheet - Page 12

• Manufacturer Part Number: MT47H64M16HR-3 IT:H
• Description: DRAM Chip DDR2 SDRAM 1G-Bit 64Mx16 1.8V 84-Pin FBGA Tray
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H64M16HR-3 IT:H

• Density: 1 Gb
• Maximum Clock Rate: 667 MHz
• Package: 84FBGA
• Operating Supply Voltage: 1.8 V
• Maximum Random Access Time: 0.45 ns
• Operating Temperature: -40 to 85 °C
• Organization: 64Mx16
• Address Bus: 16b
• Access Time (max): 450ps
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 135mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Functional Block Diagrams
Figure 3: 256 Meg x 4 Functional Block Diagram
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. V 6/10 EN
BA0–BA2
A0–A13,
RAS#
CAS#
ODT
WE#
CKE
CK#
CS#
CK
17
Address
register
registers
Mode
Control
logic
17
counter
Refresh
14
11
The DDR2 SDRAM is a high-speed CMOS, dynamic random access memory. It is inter-
nally configured as a multibank DRAM.
3
14
address
Row-
MUX
2
14
control
Bank
logic
Column-
counter/
address
latch
decoder
address
Bank 0
row-
latch
and
Bank 1
Bank 2
Bank 3
Bank 4
9
2
16,384
Bank 5
Bank 6
Bank 7
DM mask logic
(16,384 x 512 x 16)
I/O gating
Sense amplifiers
Memory array
Column
decoder
8,192
(x16)
512
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
12
Bank 7
COL0, COL1
CK, CK#
16
16
16
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Read
latch
CK out
WRITE
drivers
CK in
FIFO
and
4
4
4
4
Data
COL0, COL1
Mask
4
16
1Gb: x4, x8, x16 DDR2 SDRAM
MUX
generator
1
1
1
4
4
4
4
1
DQS
registers
Input
Functional Block Diagrams
DATA
4
DQS, DQS#
1
1
1
4
4
4
4
1
2
CK, CK#
4
1
DRVRS
2
DLL
RCVRS
© 2004 Micron Technology, Inc. All rights reserved.
sw1 sw2
sw1 sw2
sw1 sw2
sw1 sw2
R1
R1
R1
R1
R1
R1
ODT control
R2
R2
R2
R2
R2
R2
V
ss
Q
sw3
sw3
sw3
sw3
R3
R3
R3
R3
R3
R3
V
dd
Q
DQ0–DQ3
DQS, DQS#
DM