MT47H64M16HR-3 IT:H Micron Technology Inc, MT47H64M16HR-3 IT:H Datasheet - Page 58

• Manufacturer Part Number: MT47H64M16HR-3 IT:H
• Description: DRAM Chip DDR2 SDRAM 1G-Bit 64Mx16 1.8V 84-Pin FBGA Tray
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H64M16HR-3 IT:H

• Density: 1 Gb
• Maximum Clock Rate: 667 MHz
• Package: 84FBGA
• Operating Supply Voltage: 1.8 V
• Maximum Random Access Time: 0.45 ns
• Operating Temperature: -40 to 85 °C
• Organization: 64Mx16
• Address Bus: 16b
• Access Time (max): 450ps
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 135mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Input Slew Rate Derating
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. V 6/10 EN
For all input signals, the total
by adding the data sheet
value, respectively. Example:
t
crossing of V
a falling signal is defined as the slew rate between the last crossing of V
first crossing of V
If the actual signal is always earlier than the nominal slew rate line between shaded
“V
(page 61)).
If the actual signal is later than the nominal slew rate line anywhere between the sha-
ded “V
AC level to DC level is used for the derating value (see Figure 24 (page 61)).
t
crossing of V
ing signal, is defined as the slew rate between the last crossing of V
crossing of V
If the actual signal is always later than the nominal slew rate line between shaded “DC
to V
(page 62)).
If the actual signal is earlier than the nominal slew rate line anywhere between shaded
“DC to V
level to V
Although the total setup time might be negative for slow slew rates (a valid input signal
will not have reached V
input signal is still required to complete the transition and reach V
For slew rates in between the values listed in Table 29 (page 59) and Table 30
(page 60), the derating values may obtained by linear interpolation.
IS, the nominal slew rate for a rising signal, is defined as the slew rate between the last
IH, the nominal slew rate for a rising signal, is defined as the slew rate between the last
REF(DC)
REF(DC)
REF(DC)
REF(DC)
REF(DC)
to AC region,” use the nominal slew rate for the derating value (Figure 23
region,” use the nominal slew rate for the derating value (Figure 25
REF(DC)
IL(DC)max
REF(DC)
to AC region,” the slew rate of a tangent line to the actual signal from the
region,” the slew rate of a tangent line to the actual signal from the DC
level is used for the derating value (Figure 26 (page 62)).
IL(AC)max
.
and the first crossing of V
and the first crossing of V
IH[AC]
t
.
IS (base) and
/V
t
58
t
IS (total setup time) =
IS (setup time) and
IL[AC]
at the time of the rising clock transition), a valid
t
Micron Technology, Inc. reserves the right to change products or specifications without notice.
IH (base) value to the Δ
IH(AC)min
1Gb: x4, x8, x16 DDR2 SDRAM
REF(DC)
t
IH (hold time) required is calculated
t
IS (base) + Δ
Input Slew Rate Derating
. Setup nominal slew rate (
.
t
IH, nominal slew rate for a fall-
© 2004 Micron Technology, Inc. All rights reserved.
t
IS and Δ
t
IS.
IH(AC)
IH(DC)min
REF(DC)
/V
t
IH derating
IL(AC)
and the first
and the
.
t
IS) for