MT47H64M16HR-3 IT:H Micron Technology Inc, MT47H64M16HR-3 IT:H Datasheet - Page 7

• Manufacturer Part Number: MT47H64M16HR-3 IT:H
• Description: DRAM Chip DDR2 SDRAM 1G-Bit 64Mx16 1.8V 84-Pin FBGA Tray
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H64M16HR-3 IT:H

• Density: 1 Gb
• Maximum Clock Rate: 667 MHz
• Package: 84FBGA
• Operating Supply Voltage: 1.8 V
• Maximum Random Access Time: 0.45 ns
• Operating Temperature: -40 to 85 °C
• Organization: 64Mx16
• Address Bus: 16b
• Access Time (max): 450ps
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 135mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

List of Figures
Figure 1: 1Gb DDR2 Part Numbers ................................................................................................................... 2
Figure 2: Simplified State Diagram ................................................................................................................... 9
Figure 3: 256 Meg x 4 Functional Block Diagram ............................................................................................. 12
Figure 4: 128 Meg x 8 Functional Block Diagram ............................................................................................. 13
Figure 5: 64 Meg x 16 Functional Block Diagram ............................................................................................. 14
Figure 6: 60-Ball FBGA – x4, x8 Ball Assignments (Top View) ........................................................................... 15
Figure 7: 84-Ball FBGA – x16 Ball Assignments (Top View) .............................................................................. 16
Figure 8: 84-Ball FBGA Package (8mm x 12.5mm) – x16 ................................................................................... 19
Figure 9: 60-Ball FBGA Package (8mm x 11.5mm) – x4, x8 ............................................................................... 20
Figure 10: 60-Ball FBGA (8mm x 10mm) – x4, x8 ............................................................................................. 21
Figure 11: Example Temperature Test Point Location ..................................................................................... 24
Figure 12: Single-Ended Input Signal Levels ................................................................................................... 46
Figure 13: Differential Input Signal Levels ...................................................................................................... 47
Figure 14: Differential Output Signal Levels .................................................................................................... 49
Figure 15: Output Slew Rate Load .................................................................................................................. 50
Figure 16: Full Strength Pull-Down Characteristics ......................................................................................... 51
Figure 17: Full Strength Pull-Up Characteristics ............................................................................................. 52
Figure 18: Reduced Strength Pull-Down Characteristics ................................................................................. 53
Figure 19: Reduced Strength Pull-Up Characteristics ...................................................................................... 54
Figure 20: Input Clamp Characteristics .......................................................................................................... 55
Figure 21: Overshoot ..................................................................................................................................... 56
Figure 22: Undershoot .................................................................................................................................. 56
Figure 23: Nominal Slew Rate for
Figure 24: Tangent Line for
Figure 25: Nominal Slew Rate for
Figure 26: Tangent Line for
Figure 27: Nominal Slew Rate for
Figure 28: Tangent Line for
Figure 29: Nominal Slew Rate for
Figure 30: Tangent Line for
Figure 31: AC Input Test Signal Waveform Command/Address Balls ............................................................... 69
Figure 32: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential) ........................................... 69
Figure 33: AC Input Test Signal Waveform for Data with DQS (Single-Ended) .................................................. 70
Figure 34: AC Input Test Signal Waveform (Differential) ................................................................................. 70
Figure 35: MR Definition ............................................................................................................................... 78
Figure 36: CL ................................................................................................................................................ 81
Figure 37: EMR Definition ............................................................................................................................. 82
Figure 38: READ Latency ............................................................................................................................... 85
Figure 39: WRITE Latency ............................................................................................................................. 85
Figure 40: EMR2 Definition ........................................................................................................................... 86
Figure 41: EMR3 Definition ........................................................................................................................... 87
Figure 42: DDR2 Power-Up and Initialization ................................................................................................. 88
Figure 43: Example: Meeting
Figure 44: Multibank Activate Restriction ....................................................................................................... 92
Figure 45: READ Latency ............................................................................................................................... 94
Figure 46: Consecutive READ Bursts .............................................................................................................. 95
Figure 47: Nonconsecutive READ Bursts ........................................................................................................ 96
Figure 48: READ Interrupted by READ ........................................................................................................... 97
Figure 49: READ-to-WRITE ............................................................................................................................ 97
Figure 50: READ-to-PRECHARGE – BL = 4 ...................................................................................................... 98
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. V 6/10 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
1Gb: x4, x8, x16 DDR2 SDRAM
© 2004 Micron Technology, Inc. All rights reserved.