MT47H64M16HR-3 IT:H Micron Technology Inc, MT47H64M16HR-3 IT:H Datasheet - Page 118

• Manufacturer Part Number: MT47H64M16HR-3 IT:H
• Description: DRAM Chip DDR2 SDRAM 1G-Bit 64Mx16 1.8V 84-Pin FBGA Tray
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H64M16HR-3 IT:H

• Density: 1 Gb
• Maximum Clock Rate: 667 MHz
• Package: 84FBGA
• Operating Supply Voltage: 1.8 V
• Maximum Random Access Time: 0.45 ns
• Operating Temperature: -40 to 85 °C
• Organization: 64Mx16
• Address Bus: 16b
• Access Time (max): 450ps
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 135mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Power-Down Mode
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. V 6/10 EN
DDR2 SDRAM supports multiple power-down modes that allow significant power sav-
ings over normal operating modes. CKE is used to enter and exit different power-down
modes. Power-down entry and exit timings are shown in Figure 69 (page 119). Detailed
power-down entry conditions are shown in Figure 70 (page 121)–Figure 77 (page 124).
Table 44 (page 120) is the CKE Truth Table.
DDR2 SDRAM requires CKE to be registered HIGH (active) at all times that an access is
in progress—from the issuing of a READ or WRITE command until completion of the
burst. Thus, a clock suspend is not supported. For READs, a burst completion is defined
when the read postamble is satisfied; for WRITEs, a burst completion is defined when
the write postamble and
READ command) are satisfied, as shown in Figure 72 (page 122) and Figure 73
(page 122) on Figure 73 (page 122). The number of clock cycles required to meet
is either two or
Power-down mode (see Figure 69 (page 119)) is entered when CKE is registered low
coincident with an NOP or DESELECT command. CKE is not allowed to go LOW during
a mode register or extended mode register command time, or while a READ or WRITE
operation is in progress. If power-down occurs when all banks are idle, this mode is
referred to as precharge power-down. If power-down occurs when there is a row active
in any bank, this mode is referred to as active power-down. Entering power-down deac-
tivates the input and output buffers, excluding CK, CK#, ODT, and CKE. For maximum
power savings, the DLL is frozen during precharge power-down. Exiting active power-
down requires the device to be at the same voltage and frequency as when it entered
power-down. Exiting precharge power-down requires the device to be at the same volt-
age as when it entered power-down; however, the clock frequency is allowed to change
(see Precharge Power-Down Clock Frequency Change (page 125)).
The maximum duration for either active or precharge power-down is limited by the re-
fresh requirements of the device
entry and exit is limited by the
tained while in power-down mode: CKE LOW, a stable clock signal, and stable power
supply signals at the inputs of the DDR2 SDRAM. All other input signals are “Don’t
Care” except ODT. Detailed ODT timing diagrams for different power-down modes are
shown in Figure 82 (page 130)–Figure 87 (page 134).
The power-down state is synchronously exited when CKE is registered HIGH (in con-
junction with a NOP or DESELECT command), as shown in Figure 69 (page 119).
t
WTR/
t
CK, whichever is greater.
t
WR (WRITE-to-PRECHARGE command) or
118
t
CKE (MIN) parameter. The following must be main-
t
RFC (MAX). The minimum duration for power-down
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1Gb: x4, x8, x16 DDR2 SDRAM
Power-Down Mode
© 2004 Micron Technology, Inc. All rights reserved.
t
WTR (WRITE-to-
t
WTR