MT47H64M16HR-3 IT:H Micron Technology Inc, MT47H64M16HR-3 IT:H Datasheet - Page 125

• Manufacturer Part Number: MT47H64M16HR-3 IT:H
• Description: DRAM Chip DDR2 SDRAM 1G-Bit 64Mx16 1.8V 84-Pin FBGA Tray
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H64M16HR-3 IT:H

• Density: 1 Gb
• Maximum Clock Rate: 667 MHz
• Package: 84FBGA
• Operating Supply Voltage: 1.8 V
• Maximum Random Access Time: 0.45 ns
• Operating Temperature: -40 to 85 °C
• Organization: 64Mx16
• Address Bus: 16b
• Access Time (max): 450ps
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 135mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Precharge Power-Down Clock Frequency Change
Figure 78: Input Clock Frequency Change During Precharge Power-Down Mode
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. V 6/10 EN
DQS, DQS#
Command
Address
ODT
CK#
CKE
DM
DQ
CK
High-Z
High-Z
Valid 4
Valid
T0
t CH
power-down mode
t CK
Enter precharge
Notes:
t CL
Previous clock frequency
NOP
T1
When the DDR2 SDRAM is in precharge power-down mode, ODT must be turned off
and CKE must be at a logic LOW level. A minimum of two differential clock cycles must
pass after CKE goes LOW before clock frequency may change. The device input clock
frequency is allowed to change only within minimum and maximum operating frequen-
cies specified for the particular speed grade. During input clock frequency change, ODT
and CKE must be held at stable LOW levels. When the input clock frequency is changed,
new stable clocks must be provided to the device before precharge power-down may be
exited, and DLL must be reset via MR after precharge power-down exit. Depending on
the new clock frequency, additional LM commands might be required to adjust the CL,
WR, AL, and so forth. Depending on the new clock frequency, an additional LM com-
mand might be required to appropriately set the WR MR9, MR10, MR11. During the
DLL relock period of 200 cycles, ODT must remain off. After the DLL lock time, the
DRAM is ready to operate with a new clock frequency.
1. A minimum of 2 ×
2. When the new clock frequency has changed and is stable, a minimum of 1 ×
2 x t CK (MIN) 1
ing clock frequencies.
quired prior to exiting precharge power-down.
T2
t CKE (MIN) 3
T3
Frequency
Precharge Power-Down Clock Frequency Change
change
t
CK is required after entering precharge power-down prior to chang-
Ta0
125
1 x t CK (MIN) 2
t CH
power-down mode
t CK
Exit precharge
t CL
NOP
Ta1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
New clock frequency
1Gb: x4, x8, x16 DDR2 SDRAM
NOP
t XP
Ta2
t CKE (MIN) 3
DLL RESET
Ta3
LM
Indicates a break in
time scale
© 2004 Micron Technology, Inc. All rights reserved.
200 x t CK
NOP
Ta4
t
Don’t Care
Valid
Valid
CK is re-
Tb0