MT47H64M16HR-3 IT:H Micron Technology Inc, MT47H64M16HR-3 IT:H Datasheet - Page 90

• Manufacturer Part Number: MT47H64M16HR-3 IT:H
• Description: DRAM Chip DDR2 SDRAM 1G-Bit 64Mx16 1.8V 84-Pin FBGA Tray
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H64M16HR-3 IT:H

• Density: 1 Gb
• Maximum Clock Rate: 667 MHz
• Package: 84FBGA
• Operating Supply Voltage: 1.8 V
• Maximum Random Access Time: 0.45 ns
• Operating Temperature: -40 to 85 °C
• Organization: 64Mx16
• Address Bus: 16b
• Access Time (max): 450ps
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 135mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. V 6/10 EN
10. Issue two or more REFRESH commands.
11. Issue a LOAD MODE command to the MR with LOW to A8 to initialize device operation
12. Issue a LOAD MODE command to the EMR to enable OCD default by setting bits E7, E8,
13. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7, E8, and
14. The DDR2 SDRAM is now initialized and ready for normal operation 200 clock cycles af-
15. DM represents DM for the x4, x8 configurations and UDM, LDM for the x16 configura-
16. A10 = PRECHARGE ALL, CODE = desired values for mode registers (bank addresses are
(that is, to program operating parameters without resetting the DLL). To access the MR,
set BA0 and BA1 LOW; remaining MR bits must be set to desired settings. Mode Register
(MR) (page 77) for all MR requirements.
and E9 to “1,” and then setting all other desired parameters. To access the EMR, set BA0
HIGH and BA1 LOW (see Extended Mode Register (EMR) (page 82) for all EMR require-
ments.
E9 to “0,” and then setting all other desired parameters. To access the extended mode
registers, EMR, set BA0 HIGH and BA1 LOW for all EMR requirements.
ter the DLL RESET at Tf0.
tion; DQS represents DQS, DQS#, UDQS, UDQS#, LDQS, LDQS#, RDQS, RDQS# for the
appropriate configuration (x4, x8, x16); DQ represents DQ0–DQ3 for x4, DQ–DQ7 for x8
and DQ0–DQ15 for x16.
required to be decoded).
90
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1Gb: x4, x8, x16 DDR2 SDRAM
© 2004 Micron Technology, Inc. All rights reserved.