MT47H64M16HR-3 IT:H Micron Technology Inc, MT47H64M16HR-3 IT:H Datasheet - Page 81

• Manufacturer Part Number: MT47H64M16HR-3 IT:H
• Description: DRAM Chip DDR2 SDRAM 1G-Bit 64Mx16 1.8V 84-Pin FBGA Tray
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H64M16HR-3 IT:H

• Density: 1 Gb
• Maximum Clock Rate: 667 MHz
• Package: 84FBGA
• Operating Supply Voltage: 1.8 V
• Maximum Random Access Time: 0.45 ns
• Operating Temperature: -40 to 85 °C
• Organization: 64Mx16
• Address Bus: 16b
• Access Time (max): 450ps
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 135mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

CAS Latency (CL)
Figure 36: CL
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. V 6/10 EN
Notes:
The CAS latency (CL) is defined by bits M4–M6, as shown in Figure 35 (page 78). CL is
the delay, in clock cycles, between the registration of a READ command and the availa-
bility of the first bit of output data. The CL can be set to 3, 4, 5, 6, or 7 clocks, depending
on the speed grade option being used.
DDR2 SDRAM does not support any half-clock latencies. Reserved states should not be
used as an unknown operation otherwise incompatibility with future versions may result.
DDR2 SDRAM also supports a feature called posted CAS additive latency (AL). This fea-
ture allows the READ command to be issued prior to
internal command to the DDR2 SDRAM by AL clocks. The AL feature is described in
further detail in Posted CAS Additive Latency (AL) (page 84).
Examples of CL = 3 and CL = 4 are shown in Figure 36; both assume AL = 0. If a READ
command is registered at clock edge n, and the CL is m clocks, the data will be available
nominally coincident with clock edge n + m (this assumes AL = 0).
DQS, DQS#
DQS, DQS#
Command
Command
1. BL = 4.
2. Posted CAS# additive latency (AL) = 0.
3. Shown with nominal
CK#
CK#
DQ
DQ
CK
CK
READ
READ
T0
T0
NOP
NOP
T1
T1
CL = 3 (AL = 0)
t
AC,
81
t
DQSCK, and
CL = 4 (AL = 0)
NOP
NOP
T2
T2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
DQSQ.
NOP
NOP
T3
T3
1Gb: x4, x8, x16 DDR2 SDRAM
DO
n
t
RCD (MIN) by delaying the
n + 1
DO
NOP
NOP
T4
T4
Mode Register (MR)
n + 2
DO
DO
n
© 2004 Micron Technology, Inc. All rights reserved.
Transitioning data
n + 1
n + 3
DO
DO
NOP
NOP
T5
T5
n + 2
DO
n + 3
DO
NOP
NOP
Don’t care
T6
T6