Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 123

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

SCC™/ESCC™ User’s Manual
Register Descriptions
5.1 INTRODUCTION (Continued)
Bit 4: Go-Active-On-Poll control bit
When Loop mode is first selected during SDLC operation,
the SCC connects RxD to TxD with only gate delays in the
path. The SCC does not go on-loop and insert the 1-bit de-
lay between RxD and TxD until this bit has been set and
an EOP received. When the SCC is on-loop, the transmit-
ter does not go active unless this bit is set at the time an
EOP is received. The SCC examines this bit whenever the
transmitter is active in SDLC Loop mode and is sending a
flag. If this bit is set at the time the flag is leaving the Trans-
mit Shift register, another flag or data byte (if the transmit
buffer is full) is transmitted.
If the Go-Active-On-Poll bit is not set at this time, the trans-
mitter finishes sending the flag and reverts to the 1-Bit De-
lay mode. Thus, to transmit only one response frame, this
bit is reset after the first data byte is sent to the SCC, but
before CRC has been transmitted. If the bit is not reset be-
fore CRC is transmitted, extra flags are sent, slowing down
response time on the loop. If this bit is reset before the first
data is written, the SCC completes the transmission of the
present flag and reverts to the 1-Bit Delay mode.
After gaining control of the loop, the SCC is not able to
transmit again until a flag and another EOP are received.
It is good practice to set this bit only upon receipt of a poll
5-16
Manchester
NRZI
Data
NRZ
FM1
FM0
1
Figure 5-13. NRZ (NRZI), FM1 (FM0) Timing
1
0
frame to ensure that the SCC does not go on-loop without
the CPU noticing it.
In synchronous modes other than SDLC with the Loop
Mode bit set, this bit is set before the transmitter goes ac-
tive in response to a received sync character.
This bit is always ignored in Asynchronous mode and Syn-
chronous modes unless the Loop Mode bit is set. This bit
is reset by a channel or hardware reset.
Bit 3: Mark//Flag Idle line control bit
This bit affects only SDLC operation and is used to control
the idle line condition. If this bit is set to 0, the transmitter
send flags as an idle line. If this bit is set to 1, the transmit-
ter sends continuous 1s after the closing flag of a frame.
The idle line condition is selected byte by byte i.e., either a
flag or eight 1s are transmitted. The primary station in an
SDLC loop should be programmed for Mark Idle to create
the EOP sequence. Mark Idle must be deselected at the
beginning of a frame before the first data is written to the
SCC, so that an opening flag is transmitted. This bit is ig-
nored in Loop mode, but the programmed value takes ef-
fect upon exiting the Loop mode. This bit is reset by a
channel or hardware reset.
0
1
0
UM010901-0601