Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 307

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

SCC™/ESCC™ User’s Manual
Zilog SCC
Q. Do you need to clear the reset bit in WR0 after a
A. The reset is clocked with PCLK; so it must be active
Q. How long after a hardware reset should you wait
A. Four PCLKs.
Clocks
Q. Does PCLK have to have a 50% duty cycle?
A. The duty cycle doesn’t have to be 50% as long as the
Q. Can the SCC PCLK be stretched?
A. Yes, as long as the pertinent specification is met. How-
Q. The bit rate generator is driven from what sourc-
A. It may be driven from the RTxC pin or PCLK, or from a
Q. How do you connect a bit rate crystal to the SCC?
A. A crystal can be connected between RTxC and SYNC
Q. What is the crystal specification?
A. It is a fundamental, parallel resonant crystal. For fur-
Q. Can RTxC on both channels be driven from the
A. No. A separate crystal should be used for each chan-
Q. How do you select a crystal frequency?
A. Time constant: (Clock Frequency/2 x Bit rate x clock
7-2
HARDWARE CONSIDERATIONS (Continued)
es?
same crystal.
software reset?
during reset.
before programming the SCC.
minimum specification is met.
ever, this could cause a problem if PCLK is used to
generate the bit rate.
crystal.
to supply the clock if the SCC is programmed for
WR11 D7-1.
ther details see the “Design Considerations Using
Quartz Crystals with Zilog’s Components” Application
Note.
nel. The crystal should be connected between
/SYNC and RTxC of the respective channels. The al-
ternate solution may be to use crystal on one channel
and reflect the clock out of the TRxC output and feed
it into another channel.
factor) - 2. Two examples are given below:
Q. Why does the SCC initialization require that the
A. Because of the possibility of noise causing an interrupt
Q. Why are there different Clock factors?
A. These clock factors enable the SCC to sample the
Q. How is the error in the receive/transmit clock
A. The ideal way to reduce this error is by adjusting the
Q. What are the maximum transfer rates?
A. The following table shows the PCLK rates (in bps).
Bit Rate
For PCLK = 3.6864 MHz
38400
19200
9600
7200
4800
3600
2400
1200
External Status Interrupts be reset twice?
pending bit (IP) to be set. The second reset guarantees
that the latch is clear. If the latch is closed high and the
external signal is low, the first reset will open the latch
at the high-to-low transition causing an interrupt.
center of the data cell. In the 16x mode, the SCC di-
vides the bit cell into 16 counts and samples on count
8. Clock factors are generally only used with Asyn-
chronous modes.
reduced?
crystal frequency such that only an integer value of TC
is yielded when the equation is used.
1534
190
254
382
510
766
TC
46
94
Error
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For PCLK = 3.9936 MHz
Bit Rate
19200
134.5
9600
7200
4800
3600
2400
2000
1800
1200
600
300
150
110
75
50
13310
14844 .0007%
18151 .0015%
26622
39934
UM010901-0601
1107
1662
3326
6654
102
206
275
414
553
830
996
TC
Error
.06%
.04%
.03%
12%
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