Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 19

IC 10MHZ Z8500 CMOS SCC 40-DIP

Z85C3010PSG

Manufacturer Part Number
Z85C3010PSG
Description
IC 10MHZ Z8500 CMOS SCC 40-DIP
Manufacturer
Zilog
Series
SCCr
Datasheets

Specifications of Z85C3010PSG

Processor Type
Z80
Features
Error Detection and Multiprotocol Support
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Cpu Speed
8MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
85
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3934
Z85C3010PSG

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A//B. Channel A/Channel B (input). This signal selects the
channel in which the read or write operation occurs. High
selects channel A and Low selects channel B.
D//C. Data/Control Select (input). This signal defines the
type of information transferred to or from the Z85X30.
High means data is being transferred and Low indicates
a command.
1.4.3 Pin Descriptions, (Z80X30 Only)
AD7-AD0. Address/Data Bus (bidirectional, active High,
tri-state). These multiplexed lines carry register addresses
to the Z80X30 as well as data or control information to and
from the Z80X30.
R//W. Read//Write (input, read active High). This signal
specifies whether the operation to be performed is a read
or a write.
© 1998 by Zilog, Inc. All rights reserved. No part of this
document may be copied or reproduced in any form or by
any means without the prior written consent of Zilog, Inc.
The information in this document is subject to change
without notice. Devices sold by Zilog, Inc. are covered by
warranty and patent indemnification provisions appearing
in Zilog, Inc. Terms and Conditions of Sale only.
ZILOG, INC. MAKES NO WARRANTY, EXPRESS,
STATUTORY,
REGARDING THE INFORMATION SET FORTH HEREIN
OR REGARDING THE FREEDOM OF THE DESCRIBED
DEVICES
INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY
OF MERCHANTABILITY OR FITNESS FOR ANY
PURPOSE.
UM010901-0601
FROM
IMPLIED
INTELLECTUAL
OR
BY
DESCRIPTION,
PROPERTY
/CS0. Chip Select 0 (input, active Low). This signal is
latched concurrently with the addresses on AD7-AD0 and
must be active for the intended bus transaction to occur.
CS1. Chip Select 1 (input, active High). This second select
signal must also be active before the intended bus trans-
action can occur. CS1 must remain active throughout the
transaction.
/DS. Data Strobe (input, active Low). This signal provides
timing for the transfer of data into and out of the Z80X30.
If /AS and /DS are both Low, this is interpreted as a reset.
/AS. Address Strobe (input, active Low). Address on AD7-
AD0 are latched by the rising edge of this signal.
Zilog, Inc. shall not be responsible for any errors that may
appear in this document. Zilog, Inc. makes no commitment
to update or keep current the information contained in this
document.
Zilog’s products are not authorized for use as critical
components in life support devices or systems unless a
specific written agreement pertaining to such intended use
is executed between the customer and Zilog prior to use.
Life support devices or systems are those which are
intended for surgical implantation into the body, or which
sustains life whose failure to perform, when properly used
in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in
significant injury to the user.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
FAX 408 370-8056
Internet: http://www.zilog.com
SCC™/ESCC™ User’s Manual
General Description
1-9
1

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