Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 13
Z85C3010PSG
Manufacturer Part Number
Z85C3010PSG
Description
IC 10MHZ Z8500 CMOS SCC 40-DIP
Manufacturer
Zilog
Series
SCCr
Specifications of Z85C3010PSG
Processor Type
Z80
Features
Error Detection and Multiprotocol Support
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Cpu Speed
8MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
85
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3934
Z85C3010PSG
Z85C3010PSG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z85C3010PSG
Manufacturer:
Zilog
Quantity:
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Company:
Part Number:
Z85C3010PSG
Manufacturer:
Zilog
Quantity:
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UM010901-0601
The Z85C30 CMOS SCC has added new features, while
maintaining 100% hardware/software compatibility. It has
the following new features:
Some of the features listed above are available by de-
fault, and some of them (features with “*”) are disabled on
default.
New programmable WR7' (write register 7 prime) to
enable new features.
Improvements to support SDLC mode of synchronous
communication:
–
–
–
–
–
–
–
–
–
–
Improved AC timing:
–
–
–
–
Other features include:
–
–
–
Improved functionality to ease sending back-to
back frames
Automatic SDLC opening Flag transmission*
Automatic Tx Underrun/EOM Latch reset in SDLC
mode*
Automatic /RTS deactivation*
TxD pin forced “H” in SDLC NRZI mode after
closing flag*
Complete CRC reception*
Improved response to Abort sequence in status
FIFO
Automatic Tx CRC generator preset/reset
Extended read for write registers*
Write data setup timing improvement
Three to 3.5 PCLK access recovery time.
Programmable /DTR//REQ timing*
Elimination of write data to falling edge of /WR
setup time requirement
Reduced /INT timing
Extended read function to read back the written
value to the write registers*
Latching RR0 during read
RR0, bit D7 and RR10, bit D6 now has reset
defaultvalue.
ESCC (Enhanced SCC) is pin and software compati-
ble to the CMOS version, with the following additional
enhancements.
Deeper transmit FIFO (4 bytes)
Deeper receive FIFO (8 bytes)
Programmable FIFO interrupt and DMA request level
Seven enhancements to improve SDLC link layer
supports:
–
–
–
–
–
–
–
–
Delayed bus latching for easier microprocessor
interface
New programmable features added with Write Register
7' (WR seven prime)
Write registers 3, 4, 5 and 10 are now readable
Read register 0 latched during access
DPLL counter output available as jitter-free transmitter
clock source
Enhanced /DTR, /RTS deactivation timing
Automatic transmission of the opening flag
Automatic reset of Tx Underrun/EOM latch
Deactivation of /RTS pin after closing flag
Automatic CRC generator preset
Complete CRC reception
TxD pin automatically forced high with NRZI
encoding when using mark idle
Status FIFO handles better frames with an
ABORT
Receive FIFO automatically unlocked for special
receive interrupts when using the SDLC status
FIFO
SCC™/ESCC™ User’s Manual
General Description
1-3
1
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