Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 220

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

UM010901-0601
TRANSMIT OPERATION
To transmit a block of data, the main program calls up the
transmit data routine. With this routine, each message
block to be transmitted is stored in memory, beginning with
location ‘TBUF’. The number of characters contained in
each block is determined by the value assigned to the
‘COUNT’ parameter in the main module.
To prepare for transmission, the routine enables the
transmitter and selects the Wait On Transmit function; it
then enables the wait function. The Wait On Transmit
function indicates to the CPU whether or not the Z-SCC is
ready to accept data from the CPU. If the CPU attempts to
send data to the Z-SCC when the transmit buffer is full, the
Z-SCC asserts its Wait line and keeps it Low until the
buffer is empty. In response, the CPU extends its I/O
cycles until the Wait line goes inactive, indicating that the
Z-SCC is ready to receive data.
The CRC generator is reset and the Transmit CRC bit is
enabled before the first character is sent, thus including all
RECEIVE OPERATION
Once the Z-SCC is initialized, it can be prepared to receive
data. First, the receiver is enabled, placing the Z-SCC in
Hunt mode and thus setting the Sync/Hunt bit in status
register RR0 to 1. In Hunt mode, the receiver is idle except
that it searches the incoming data stream for a sync
character match. When a match is discovered between the
incoming data stream and the sync characters stored in
WR6 and WR7, the receiver exits the Hunt mode, resetting
the Sync/Hunt bit in status register RR0 and establishing
the Receive Interrupt On First Character mode. Upon
detection of the receive interrupt, the CPU generates an
Interrupt Acknowledge cycle. The Z-SCC sends to the
CPU vector %2C, which points to the location in the
Program Status Area from which the receive interrupt
service routine is accessed.
The receive data routine is called from within the receive
interrupt service routine. While expecting a block of data,
the Wait On Receive function is enabled. Receive data
buffer RR8 is read, and the characters are stored in
memory locations starting at RBUF. The Start of Text
(%02) character is discarded. After the End of
SOFTWARE
Software routines are presented in the following pages.
These routines can be modified to include various versions of
Bisync protocol, such as Transparent and Nontransparent
the characters sent to the Z-SCC in the CRC calculation,
until the Transmit CRC bit is disabled. CRC generation can
be disabled for a particular character by resetting the
TxCRC bit within the transmit routine. In this application,
however, the Transmit CRC bit is not disabled, so that all
characters sent to the Z-SCC are included in the CRC
calculation.
The Z-SCC’s transmit underrun/EOM latch must be reset
sometime after the first character is transmitted by writing
a Reset Tx Underrun/EOM command to WR0. When this
latch is reset, the Z-SCC automatically appends the CRC
characters to the end of the message in the case of an
underrun condition.
Finally, a five-character delay is introduced at the end of
the transmission, which allows the Z-SCC sufficient time to
transmit the last data byte, two CRC characters, and two
sync characters before disabling the transmitter.
Transmission character (%04) is received, the two CRC
bytes are read. The result of the CRC check becomes valid
two characters later, at which time, RR1 is read and the
CRC error bit is checked. If the bit is zero, the message
received can be assumed correct; if the bit is 1, an error in
the transmission is indicated.
Before leaving the interrupt service routine, Reset Highest
IUS (Interrupt Under Service), Enable Interrupt on Next
Receive Character, and Enter Hunt Mode commands are
issued to the Z-SCC.
If a receive overrun error is made, a special condition
interrupt occurs. The Z-SCC presents the vector %2E to
the CPU, and the service routine located at address
%447A is executed. The Special Receive Condition
register RR1 is read to determine which error occurred.
Appropriate action to correct the error should be taken by
the user at this point. Error Reset and Reset Highest IUS
commands are given to the Z-SCC before returning to the
main program so that the other lower priority interrupts can
occur.
modes. Encoding methods other than NRZ (e.g., NRZI, FM0,
FM1) can also be used by modifying WR10.
SCC in Binary Synchronous Communications
Application Note
6-85
9