Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 224

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

UM010901-0601
TRANSMIT ROUTINE
SEND A BLOCK OF DATA CHARACTERS
THE BLOCK STARTS AT LOCATION TBUP
OA6
00A6
00AB
00AA
00AC
00AE
00B0
00B2
00B4
00B6
00B8
00BA
00BC
00BE
00C0
00C2
00C4
00C6
00C8
00CA
00CC
00CE
00D0
00D2
00D4
00D6
00D8
00DA
00DC
00DE
00E0
00E2
00E4
00E6
00E8
00EA
00EC
00EE
00F0
00F2
00F4
2102
0028'
C86C
3AB6
FE2B
C800
3A86
FE23
C888
3AB6
FE23
C880
3A86
FE21
2101
FE31
C86D
3A86
FE2B
2100
0001
3A22
0010
C8C0
3AB6
FE21
2100
000B
3A22
0010
C804
3EI8
2100
0686
F081
C800
3AB6
FE2B
9E0B
GLOBAL
ENTRY
DEL:
END TRANSMIT
TRANSMIT
LD
LDB
OUTB
LDB
OUTB
LDB
OUTB
LDB
OUTB
LD
LDB
OUTB
LD
OTIRB
LDB
OUTB
LD
OTIRB
LDB
OUTB
LD
DJNZ
LDB
OUTB
RET
PROCEDURE
R2, #TBUF
RL0, #%6C
WR0A+10, RL0
RL0, #%00
WR0A+2 , RL0
RL0, #%88
WR0A+2, RL0
RL0, #%80
WR0A, RL0
R1, #WR0A+16
RL0, #%6D
WR0A+10, RL0
R0, #1
@Rl, @R2,R0
RL0, #%C0
WR0A, RL0
R0, #COUNT-1
@Rl, @R2, R0
RL0, #%04
@R1, RL0
R0, #1670
R0, DEL
RL0, #0
WR0A+10, RL0
!PTR TO START OF BUFFER!
!ENABLE TRANSMITTER!
!WAIT ON TRANSMIT!
!WAIT ENABLE, INT ON 1ST & SP COND!
!RESET TxCRC GENERATOR!
!WR8A SELECTED!
!Tx CRC ENABLE!
!SEND START OF TEXT!
!RESET TxUND/EOM LATCH!
!SEND MESSAGE!
!SEND END OF TRANSMISSION CHARACTER!
!CREATE DELAY BEFORE DISABLING!
!DISABLE TRANSMITTER!
SCC in Binary Synchronous Communications
Application Note
6-89
9