Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 306

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

UM010901-0601
HARDWARE CONSIDERATIONS
This section includes questions and answers on the hard-
ware interface, the clocks, the FIFO, special modes (Local
Loopback, DPLL, Manchester), and internal timing consid-
eration.
Hardware (Includes DMA Interface)
Q. What is the SCC transistor count?
A. Approximately 6000 gates, or 18,000 transistors.
Q. What is the difference between the Z8030 and the
A. The Z8030 and Z8530 are packaged from the same
Q. Can /AS be active only when the Z8030 is being ac-
A. Since the interrupt pending bits (IPs) are updated on
Q. How do /WR and /CE interact on the Z8530?
A. /WR and /CE are ANDed to enable a transparent latch.
Q. How many register pointers does the Z8530 have?
A. The SCC has only one register pointer for both chan-
Z8530?
die. The multiplexed bus (Z8030) or non-multiplexed
bus (Z8530) version of the chip is selected at packag-
ing time by an internal bonding option.
cessed and High all other times?
address strobes, interrupts will not occur unless /AS is
continuous.
Data is latched on the falling edge when both /CE and
/WR go Low.
nels. The SIO (Z844X) has two, one for each channel.
This document addresses the most commonly asked questions about Zilog’s SCC.
Hard ware Considerations
Interrupt s and Polling
Asychronous mode
These questions fall into the following five categories:
A
Z
Z8030/Z8530
Q
Q. Do you have to write to the pointer with the Z8530
A. No. Both registers are accessed automatically without
Q. Does /CE (/CS) have to be High during an interrupt
A. No.
Q. Does the SCC support full duplex DMA?
A. The SCC allows full duplex DMA transfers by using the
Q. When using full duplex DMA, how do you program
A. W/REQ should be programmed for receive and
Q. Can both channels make simultaneous DMA
A. Yes.
Q. Do you have to reset the SCC in hardware?
A. No. A software reset is the same as a hardware reset,
PPLICATION
UESTIONS AND
ILOG
to access WR0 or RR0?
first writing to the pointer.
acknowledge cycle?
DTR/REQ and W/REQ as two separate DMA control
lines for transmit request and receive request on each
channel.
W/REQ?
DTR/REQ pin should be programmed for transmit.
requests?
(WR9 CO). It also does not matter whether the Z8030
is in shift right or shift left mode because the address
is the same in either.
Sychronous Mode
Miscellaneous Questions
SCC
N
OTES
A
NSWERS
7-1