Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 264

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

UM010901-0601
MODIFIED WRITE TIMING
In the SCC write cycle, the SCC assumes the data is valid
when /WR is asserted (Figure 15). This assumption is not
valid for some CPUs, e.g., the Intel 80X86. The /WR signal
from this CPU needs to delay for one more clock to initiate
the write cycle. Additional hardware is required.
ESCC
SCC
/WR
Databus latched after falling edge of WR saves external logic required
to delay WR until databus is valid. Typically needed with Intel CPUs.
SCC Spec:
WR Falling
Databus Va
Minimum
Figure 15. Modified Write Timing
29
Databus Valid
29
Boost Your System Performance Using The Zilog ESCC
In the ESCC, write cycle timing has been modified so that
data becomes valid a short time after write (approx. 20 ns).
Therefore, if the data pins from the Intel CPU are
connected directly to the ESCC, no additional logic is
required.
ESCC Spec:
Databus Valid to WR Falling
Databus Valid
Application Note
6-129
™
1