Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 258
Z85C3010PSG
Manufacturer Part Number
Z85C3010PSG
Description
IC 10MHZ Z8500 CMOS SCC 40-DIP
Manufacturer
Zilog
Series
SCCr
Specifications of Z85C3010PSG
Processor Type
Z80
Features
Error Detection and Multiprotocol Support
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Cpu Speed
8MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
85
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3934
Z85C3010PSG
Z85C3010PSG
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UM010901-0601
AUTOMATIC /RTS DEASSERTION
Several SDLC enhancements are provided in the ESCC.
The ESCC allows automatic /RTS deassertion at End Of
Frame (EOF). The automatic /RTS deassertion is enabled
by setting WR7' D2. If ESCC is programmed for SDLC
mode and the Flag-On-Underrun bit (WR10 D2) is reset,
with the RTS bit (WR5 D1) reset, /RTS is deasserted
automatically at the last bit of the closing flag. It is triggered
by the rising edge of the Transmit Clock (TxC - Figures 6
and 7).
TXC
TXD
/RTS
TX Underrun/EOM
(WR5, D1)
/RTS Pin
RTS Bit
Automatic RTS Pin Deactivation
Figure 7. /RTS Deassertion Sequence
Figure 6. /RTS Deassertion Timing
TX Closing
Flag
Data Being Sent
Data
Boost Your System Performance Using The Zilog ESCC
CRC1
/RTS is normally used in SDLC for switching the direction
of line drivers. Automatic /RTS deassertion allows optimal
line switching without any software intervention. The
typical procedures are as follows:
1. Enable Automatic /RTS Deassertion
2. Before frame transmission, set RTS bit
3. Enable frame transmission
4. Reset RTS bit
5. RTS pin deassertion is delayed until the last rising TxC
edge closing flag.
CRC2
Flag
Mark
Application Note
6-123
™
1
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