Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 42

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

When these bits indicate that a received character has
reached the exit location of the FIFO, the status in RR1
should be checked and then the data should be read. If
status is to be checked, it must be done before the data is
read, because the act of reading the data pops both the
data and error FIFOs.
2.4.7.3 Receive Interrupt on First Character or Special
Condition
This mode is designed for use with DMA transfers of the
receive characters. The processor is interrupted when the
SCC receives the first character of a block of data. It reads
the character and then turns control over to a DMA device
to transfer the remaining characters. After this mode is se-
lected, the first character received, or the first character al-
ready stored in the FIFO, sets the receiver IP. This IP is re-
set when this character is removed from the SCC.
No further receive interrupts occur until the processor is-
sues an Enable Interrupt on Next Receive Character com-
mand in WR0 or until a special receive condition occurs.
The correct sequence of events when using this mode is
to first select the mode and wait for the receive character
available interrupt. When the interrupt occurs, the proces-
sor should read the character and then enable the DMA to
transfer the remaining characters.
ESCC:
WR7' bit D3 should be reset to zero in this mode.
A special receive condition interrupt may occur any time
after the first character is received, but is guaranteed to oc-
cur after the character having the special condition has
been read. The status is not lost in this case, however, be-
cause the FIFO is locked by the special condition. In the in-
terrupt service routine, the processor should read RR1 to
obtain the status, and may read the data again if neces-
sary. The FIFO is unlocked by issuing an Error Reset com-
mand in WR0. If the special condition was End-of-Frame,
the processor should now issue the Enable Interrupt on
Next Receive Character command to prepare for the next
frame. The first character interrupt and special condition
interrupt are distinguished by the status included in the in-
terrupt vector. In all other respects they are identical, in-
cluding sharing the IP and IUS bits.
2.4.7.4 Interrupt on All Receive Characters or Special
Condition
This mode is designed for an interrupt driven system. In
this mode, the NMOS/CMOS version and the ESCC with
WR7' D3=0 sets the receive IP when a received character
is shifted into the exit location of the FIFO. This occurs
whether or not it has a special receive condition. This in-
cludes characters already in the FIFO when this mode is
selected. In this mode of operation the IP is reset when the
character is removed from the FIFO, so if the processor re-
quires status for any characters, this status must be read
before the data is removed from the FIFO.
UM010901-06
01
On the ESCC with D3=1, four bytes are accumulated in the
Receive FIFO before an interrupt is generated (IP is set),
and reset when the number of the characters in the FIFO
is less than four.
The special receive conditions are identical to those previ-
ously mentioned, and as before, the only difference be-
tween a “receive character available” interrupt and a “spe-
cial receive condition” interrupt is the status encoded in the
vector. In this mode a special receive condition does not
lock the receive data FIFO so that the service routine must
read the status in RR1 before reading the data.
At moderate to high data rates where the interrupt over-
head is significant, time can usually be saved by checking
for another character before exiting the service routine.
This technique eliminates the interrupt acknowledge and
the status processing, saving time, but care must be exer-
cised because this receive character must be checked for
special receive conditions before it is removed from
the SCC.
2.4.7.5 Receive Interrupt on Special Conditions
This mode is designed for use when a DMA transfers all
receive characters between memory and the SCC. In this
mode, only receive characters with special conditions will
cause the receive IP to be set. All other characters are as-
sumed to be transferred via DMA. No special initialization
sequence is needed in this mode. Usually, the DMA is ini-
tialized and enabled, then this mode is selected in the
SCC. A special receive condition interrupt may occur at
any time after this mode is selected, but the logic guaran-
tees that the interrupt will not occur until after the character
with the special condition has been read from the SCC.
The special condition locks the FIFO so that the status is
valid when read in the interrupt service routine, and it guar-
antees that the DMA will not transfer any characters until
the special condition has been serviced.
In the service routine, the processor should read RR1 to
obtain the status and unlock the FIFO by issuing an Error
Reset command. DMA transfer of the receive characters
then resumes. Figure 2-15 shows the special conditions
interrupt service routine.
Note: On the CMOS and ESCC, if the SDLC Frame Status
FIFO is being used, please refer to Section 4.4.3 on the
FIFO anti-lock feature.
Note: Special Receive Condition interrupts are generated
after the character is read from the FIFO, not when the
special condition is first detected. This is done so that
when using receive interrupt on first or Special Condition
or Special Condition Only, data is directly read out of the
data FIFO without checking the status first. If a special
condition interrupted the CPU when first detected, it would
be necessary to read RR1 before each byte in the FIFO to
determine which byte had the special condition. Therefore,
SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
2-23
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