Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 158

IC 10MHZ Z8500 CMOS SCC 40-DIP

Z85C3010PSG

Manufacturer Part Number
Z85C3010PSG
Description
IC 10MHZ Z8500 CMOS SCC 40-DIP
Manufacturer
Zilog
Series
SCCr
Datasheets

Specifications of Z85C3010PSG

Processor Type
Z80
Features
Error Detection and Multiprotocol Support
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Cpu Speed
8MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
85
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3934
Z85C3010PSG

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UM010901-0601
A SIMPLE Z80-Z8500 SYSTEM
The Z8500 devices interface easily to the Z80 CPU, thus
providing a system of considerable flexibility. Figure 16
illustrates a simple system using the Z80A CPU and Z8536
Counter/Timer and Parallel I/O Unit (CIO) in a mode 1 or
non-interrupt environment. Since interrupt vectors are not
used, the /INTACK line is tied High and no additional logic
is needed. Because the CIO can be used in a polled
interrupt environment, the /INT pin is connected to the
Additional Information in Zilog Publications:
The Z80 Family User’s Manual includes technical
information on the Z80 CPU, DMA, PIO, CTC, and SIO.
Technical information on the Z80 CPU AC Characteristics
and the Z80 Family Interrupt Structure Tutorial can be
found in the Z80 Databook.
Figure 16. Z80 to Z8500 Simple System Mode 1 Interrupt or Non-Interrupt Structure
CPU. The Z80 should not be set for mode 2 interrupts
since the CIO will never place a vector onto the data bus.
Instead, the CPU should be placed into mode 1 interrupt
mode and a global interrupt service routine can poll the
CIO to determine what caused the interrupt to occur. In this
system, the software emulation procedure described
above is effective.
The Z8000 User’s Manual features technical information
on the Z8536 CIO and Z8038 FIO.
Interfacing Z80
®
CPUs to the Z8500 Peripheral Family
Application Note
6-23
6

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